Jet vapor deposition reduces gate leakage
Engineers at Motorola have demonstrated reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. In a paper presented at the recent IEDM meeting, Hsing-Huang Tseng, et al.  showed that JVD nitride provides a robust interface and well-behaved bulk properties, MOSFET characteristics, and ring oscillator performance.
As gate oxide thickness decreases in advanced technology, leakage current through the gate oxide increases, and boron penetration in surface-channel PMOSFETs with p+ gates increases. Conventional CVD nitride has a poor interface with silicon and is leaky due to a high trap density in the film. Recent studies in JVD nitride have shown encouraging electrical results with an aluminum gate.
In Tseng`s work, devices were built using a 0.35-?m technology with shallow trench isolation, n+/p+ gates, Ti-salicide, and shallow transistor extensions with 1400-? nitride spacers. Wafers were cleaned, and JVD nitride was deposited in a single-wafer chamber. An 800? C post depositional anneal was performed prior to depositing the polysilicon gate and the completion of wafer processing.
The figure shows the TEM cross-section of the poly/JVD nitride/Si structure. The physical thickness is 50 ?, while the equivalent oxide thickness is 31 ?. The increased physical thickness, due to the high dielectric constant of nitride, resulted in 100? lower leakage current than SiO2 at a 5-MV/cm electric field.
Poly gate capacitors of JVD nitride and thermal oxide fabricated with the full CMOS process were stressed using constant current injection to a 0.5-C/cm2 fluence. The interface stability of JVD nitride compared favorably with thermal oxide. Post nitride deposition annealing played an important role in achieving a stable JVD nitride film, significantly reducing both the surface and bulk hydrogen concentration.
JVD nitride also showed strong resistance to boron penetration. In a capacitor lot with standard boron and BF2 implantation for p+ gate, normalized high frequency C-V resulted. For an n+ gate, JVD nitride revealed a negative shift compared with thermal oxide, due to the larger fixed charge contained in JVD nitride. For the p+ gate, the situation was worse. However, JVD nitride showed much less C-V shift comparing phosphorus/n+ and boron/p+ gates revealing the efficiency of boron penetration reduction. The negligible C-V difference between B and BF2 implanted p+ gate capacitors, suggested that JVD nitride has a strong resistance to fluorine-enhanced boron penetration.
In a transistor lot with aggressive p+ gate implantation conditions, JVD nitride showed a slightly lower Vt,n in an N-channel MOSFET than thermal oxide, due to the influence of the extra fixed charge. For the P-channel MOSFET, because a high nonstandard BF2 dose was implanted into the p+ gate, thermal oxide showed severe boron penetration effects, which caused a shift of the threshold voltage to a slightly positive value. The negative Vt,p for JVD nitride was partially due to strong resistance to boron penetration and to the additive effect of fixed charge and increased donor-like interface states originating from the nitride. JVD nitride provided a well behaved P-channel MOSFET I-V characteristic.
Tseng concluded that JVD nitride can be implemented for ULSI technology if manufacturing related issues are resolved. IBM and Lucent Technologies have already expressed interest in developing tools using this technology.
1. H.H. Tseng, et al., "Application of JVD nitride gate dielectric to a 0.35-micron CMOS process for reduction of gate leakage current and boron penetration," 26.6.1, IEDM Technical Digest, 1997.