Texas Instruments reports 0.06-?m gates
Researchers from Texas Instruments, in a presentation at the recent VLSI Symposium in Kyoto, Japan, reported fabrication of 0.06-?m polysilicon gates using DUV lithography. According to authors Wei W. Lee, et al., the process uses an optimized PECVD SixOyNz layer as both ARC and hardmask.
The figure illustrates the process flow. First, conventional DUV exposure creates 0.22- to 0.26-?m resist lines. Next, a plasma etch reduces the patterned resist features to < 0.1 ?m. Finally, a multiple step ARC/poly-Si etch creates the poly-Si features.
The SixOyNz layer is critical to the linewidth reduction etch. According to Lee, similar techniques have been used with both LPCVD SiNx and organic ARC layers, but these approaches will not work for sub-0.1-?m gates. Nonuniform gas distribution in LPCVD SiNx systems causes unacceptable optical nonuniformity. Moreover, organic ARC layers have higher substrate reflectivity, undercutting the resist profile, and also have poor etch selectivity to resist.
SixOyNz resolves both these issues. Varying the deposition gas flow ratios allows tuning of the refractive index to optimize the ARC reflectivity and thickness. The high selectivity of SixOyNz to resist both prevents damage to the resist top surface during the linewidth reduction etch and protects the poly-Si lines in areas where the resist thickness is marginal. Suppression of substrate reflections and the etch selectivity of SixOyNz, Lee said, allowed fabrication of sub-0.1-?m gates with excellent CD control. - K.D.
 |
Figure: Sub-0.1-?m linewidth reduction process with a) SiON ARC and b) organic ARC.
Print
Email
Save
