Plate design and cost of ownership for in-process FPD test systems
Ying-Moh Liu, Photon Dynamics, Milpitas, California
This paper will discuss the tradeoffs in flat panel display (FPD) plate design strategies, such as the use of 1G1D (1 gate, 1 data) or 2G2D (2 gate, 2 data) shorting bars, and their impact on test coverage, throughput, probing requirements, and other factors that can affect the total cost of ownership (COO).
As the active matrix liquid crystal display (AMLCD) market grows, flat panel manufacturers are facing multinational competition on pricing, performance and quality. This trend has pushed the panel manufacturers to use complex array testers and other back-end inspection machines to improve their process yields and reduce per-unit costs. Techniques that provide thorough testing at a low cost are critical for optimum FPD manufacturing.
The AMLCD FPD manufacturing process
Manufacturing a typical AMLCD involves three principal steps. First, an active array of thin film transistors (TFT) is built on a glass substrate through a photolithography process similar to those used for semiconductor devices. Then, a color filter is attached on top of the transistor-embedded substrate and liquid crystal material is injected between the color filter and the transistor array. The color filter selectively filters out the light emissions from each multicolor pixel array to produce the desired color mix in the video image. Finally, the display is packaged and necessary driver electronics are attached. The driver electronics interpret and convert the signals sent by the computer or other electronic system and cause the AMLCD to display the desired text and video images.
While there are some similarities between the techniques used to manufacture semiconductor devices and FPDs, the manufacture of FPDs is different in a number of ways that expose the manufacturer to potentially greater risks of yield loss. Materials represent a much larger percentage of the total FPD manufacturing cost. Nearly 80% of the overall cost of a typical full-color AMLCD is incurred in the later stages of the process, after the primary array has been developed on the substrate. Improved FPD yields depend in large part on manufacturers` ability to test and inspect displays both during and upon completion of the manufacturing process and to use test and inspection data to define the manufacturing process. Through in-process testing, the manufacturer seeks to identify defects at an early stage in order to permit repair or to avoid wasting costly materials on continued manufacturing of a defective product. Significant yield improvements can result if defects can be properly detected and characterized early in the process.
An effective array tester needs to be able to handle large plates with a high number of panel counts/plate and provide fast throughput without sacrificing defect coverage. The voltage imaging technique [1-8] has been used to test active arrays by imposing panel driving signals on the shorting bars, which are commonly used in array design to minimize electrostatic discharge (ESD) damage. The imager uses an electro-optical modulator that is sensitive to minute variations in electrical fields and is placed above a portion of an energized array. The modulator reflects or scatters light, depending on the strength of discrete electrical fields produced by the voltages of the individual pixels in the test area. Through the use of a specialized camera, digitial image processing software, and signal processing, a video image replicating the voltage of each pixel on the array is produced. This video signal is then converted into graphical and numerical data for individual pixel voltages and used to detect and characterize defects. The technique allows highly sensitive, noncontact, true functional testing of TFT arrays on AMLCD substrate panels.
Figure 1. a) Panel with basic 2G2D configuration; b) alternative scheme in full interdigitation but with bonding on one side and probing at far corners; c) 2G2D configuration with panel shorting bars all on one side to minimize required real estate; d) 1G2D configuration with panel shorting bars all on one side to minimize required real estate; e) 2G1D configuration with panel shorting bars all on one side to minimize required real estate; f) 1G1D configuration.
Shorting bars are commonly used in array design to minimize ESD damage. Each shorting bar connects a set of gate (G) or data (D) bus lines. All of the shorting bars are tied together by connecting an appropriate resistor between any two of them. In case of a voltage surge, this design allows current to flow throughout the panel and not create a localized high electric field, which could damage the panel pixels. The simplicity and reliability of the panel probing interface leads to lower cost, short changeover time, high mean time between failures (MTBF), low mean time to repair (MTTR), and ease of maintenance, all related to COO.
This paper will introduce some basic considerations in designing an active plate for optimum testability, present a few examples of shorting bar configurations, and provide a test coverage comparison between different configurations. A COO model and comparison data from internal studies conducted by Photon Dynamics Inc. will illustrate the best strategy when selecting a test system.
Defect coverage for different panel designs
Manufacturers must consider plate design as an element in low-cost array testing. Panel designs with 1G1D line shorting bars have the least defect coverage. Short defects are not detectable because all the pixels are basically shorted by the single shorting bar. To increase detectable defect types, the panel shorting bars need to be better multiplexed. Panels with 1G1D plus 1 common (1C) will have increased defect detectability, as do 1G2D, 2G1D, 2G2D, or even 2G3D. Examples of these panel shorting bar configurations are given in Fig. 1a-f.
Figure 2. Illustration of defects detectable by the voltage imaging test systems.
Figure 1a, the fundamental layout for a panel with 2G2D shorting bars, shows that the 2 gate shorting bars are placed with 1 at the left and 1 at the right side of the panel. The signal line contact pads are placed on all four sides of the panel, which complicates the glass cutting and tape automated bonding (TAB) processes. The layout shown in Fig. 1b was created to place the bonding pads at only two of the four sides of the panel, but four cuts are still needed to discard the shorting bars during cell assembly.
In a simplified layout (Fig. 1c), both gate shorting bars are placed at the same side of the panel. The same is done for the 2 data line shorting bars. Note that either the odd or the even signal lines need to go under or above the shorting bar that is closer to the panel, so that electrical isolation can be ensured in the layout and signals do not get mixed up. At the next level of simplification, (Fig. 1d and 1e), there is only 1 gate shorting bar or 1 data shorting bar, respectively. The availability of this kind of layout is largely determined by the available real estate on the substrate; the additional shorting bar does take a little more space on the glass. The last simplification (Fig. 1f) minimizes the needed space by using only 1 gate and 1 data shorting bars.
The defect detectability of 1G1D, 1G2D and 2G2D layouts are summarized in Table 1 and the defects listed are illustrated in Fig. 2. The 2G2D design offers the most complete defect coverage and is the most highly recommended panel design.
Plate and tester design considerations
Many issues need to be considered when designing an active array plate for testability (Table 2), but economical use of resources is a fundamental requirement. The voltage imaging technique uses the ESD protection shorting bars to apply drive signals to the panel pixels. Since this scheme requires at most a few contacts on each shorting bar, the total number of contacts/panel is usually about 10 to 20. The probe frame design is relatively simple and the changeover time, the time required to change the test system to test a different panel type, is as short as 30 minutes.
This simple probe frame also has inherently high reliability. Since the pin separation is large (~10 mm) and the contact pin density is low, there is no pin-to-pin short problem (common in full contact probe cards) to introduce false line defects. Such false defects are not acceptable - panels with more than one or two line defects are commonly rejected. With proper plate design, the simple probe frame allows testing of multiple panel types, eliminating the changeover time, and reducing tooling and running costs.
Optimum plate layout for testing with voltage imaging
As shown in Fig. 3a, a plate can be laid out so that all the contact pads are located at the outer edges. The shorting bars are connected to the contact pads via the routing traces as shown in Fig. 3b. In order to obtain evenly driven odd and even lines, the line impedances from the contact pad to the mid-point of the even and odd shorting bars need to be about the same.
Cost of ownership
The semiconductor equipment industry has adopted cost of ownership as a standard method to compare different products when their quality, performance, reliability, and price all vary. Even though it is the only unbiased measure of the true benefit of a piece of equipment, cost of ownership has not gained an equivalent acceptance in the FPD or LCD equipment industry. This article, however, applies the COO model developed by SEMI [9, 10] to TFT array testing methodologies and systems.
COO involves much more than just the initial purchase price of the equipment. Over the usable life of the system, there are annual costs or variable costs including material, labor, maintenance, service contracts, utilities, tooling, and overhead expenses. The reliability of the system translates to usable hours per year: a higher-reliability system tests more panels. A test system that finds more types of defects will reduce waste of materials and thus reduce total manufacturing cost. Obviously, system throughput is another important factor.
Test coverage measures the types of defects that can be detected by a specific test system. Combined with the percentages of occurrence of different defect types, we can estimate the mis-test rate and the costs associated with mis-testing good (a cost) and bad (b cost) panels. The determination of test strategy, decision to test, and choice of system all become more complicated issues than simply comparing list prices from equipment suppliers.
The COO model needs to include the following costs:
Equipment cost - system purchase price + depreciation, etc.
Operating cost - including material, labor, maintenance, service contracts, utilities, tooling, and overhead expenses
Down time - MTBF, MTTR
Value of components (such as color filter)
Cost of discarding a good panel (a cost)
Cost of shipping a bad panel (b cost)
Figure 3. a) Example of an optimum plate design with all contact pads on the periphery; b) example of a panel shorting bar via routing traces to allow contacts on the glass periphery
Although most manufacturers and the media have focused on the design and reliable manufacture of the TFT array, most of the cost of a TFT SVGA display is incurred after completion of the array . These costs include the color filter, driver IC chips, labor cost, and production equipment utilization costs. The color filter costs about $100 for each 10.4-in. or 12.1-in. super video graphics array (SVGA) panel, and the labor and other production equipment used in completing defective panels are also substantial. For example, we can assume a TFT production of 2,400,000 panels/year in a fab, with a line yield of 85%. Without array testing, the 15% defective panels would be processed through the cell assembly step to add the color filter. The 15% defective panels will thus waste color filters worth US $36 million.
Defect types and probability distribution
During TFT active array fabrication, it is common to find pixel defects, line defects, cluster defects, and half-tone pixel defects. Similar types of defects may be added to an originally good TFT array during cell assembly. Finally, other types of defects are introduced in the cell assembly due to the addition of liquid crystal (LC). These defects often manifest themselves as low-contrast defects, known as "Mura" .
From an industry survey , the percentages of defect types found in completed panels are given in Table 3. As indicated, defects are assumed to occur during array fabrication, cell assembly, and module assembly. The total defect probability at each process step is
D1 = % of defects occurred at array fabrication= P1 + P2 + P3 + (% of breakage at TFT testing, P5/3)= 0.326+0.247+0.077+0.01 = 0.66(1)
D2 = % of defects occurred at cell assembly
= P4 + (% of breakage at cell assembly, P5/3) + (half of other yield loss, P6/2)
= 0.061+0.01+0.12 = 0.191 (2)
D3 = % of defects occurred at module assembly
= (half of other yield loss, P6/2) + (remaining % breakage)
= 0.12 + 0.029 = 0.149 (3)
COO model without array tests (i = 1)
The first option when selecting an array tester is not to use one at all. All TFT plates from the front-end process are sent to cell assembly, and tests are performed at this stage. Capital investment on testers will be used on costs incurred by material waste instead. For COO definitions, see "Definitions for COO model."
First, let`s assume that the yield of the TFT fabrication process is Y1 and the yield of the cell assembly is Y2. When there are no array tests, the portion of TFT panels with defects, (1- Y1), will proceed to the cell assembly, which will then generate defective cells. The scrap cost is the sum of TFT array cost (Vp), the color filter cost (Vf), and the labor and material cost in the cell assembly process. The scrap and overhead cost, C1, is thus,
where W = the total number of panels fabricated in a year.
The first term in Eqn. 4 represents the cost of defective cells generated by the defective TFT arrays, and the second term is from the defective cells due to errors in the cell assembly process.
COO model with array tests using voltage imaging testing (i = 2)
Voltage imaging testing systems identify the location and qualitative characterization of each defect, and are capable of measuring voltage levels of each individual pixel on the array. Only very few contact pins/panel are used as opposed to the many thousand pins required in probing array testers. This difference means simpler design of the probe frame, which means lower cost, short design and development cycle, longer MTBF, shorter MTTR, ease of performing tests on newly developed panels, and short changeover time. All these factors lead to lower running costs. As opposed to probers, there is no need to change the machine when changing from one level of panel density and size to a much higher density and larger size panel. In such cases, the prober may require a completely different platform in order to match the tester capability to the panel.
Figure 4. Voltage imaging tester COO model.
When using voltage imaging testing to test TFT arrays before cell assembly, bad arrays with a higher than acceptable number of defects will be removed from the manufacturing flow. As a result, fewer color filters and less labor will be lost assembling bad arrays. A block diagram, shown in Fig. 4, illustrates the COO model using voltage imaging testing.
As shown in Table 4, the annual fixed cost plus variable cost for voltage imaging testing (IPT), C21, is $678,000. Since the tester can detect all types of TFT defects, all the possibly defective TFT arrays are found and rejected. The tester yield, Y21, is thus the same as the actual TFT yield, Y1. Thus, scrap cost, C22, for the TFT array is
The portion of good TFT panels, W Y1, will proceed to cell assembly. The scrap cost after cell assembly process is
Based on studies performed at customer sites, voltage imaging testing has a 0.15% error of testing good arrays as bad, and 0.25% error of passing bad panels as good due to modulator defects. The overall a2 and b2 error costs are then
The total annual cost of using voltage imaging tester is
The number of arrays tested per year, W, can be calculated using the MTBF = 750 hours and MTTR = 4 hours. Assuming the usable time of the machine in a year is 8400 hours or 350 days, the actual machine operating time, Ta, is
Assuming 40 sec/panel test time, the number of panels tested in a year, N, is
COO model for array tester using probing technique (i = 3)
A probing tester uses a probe card to contact the panel at every data line and gate line pad. For an SVGA resolution panel, there are 600 ? 2400 pads, which accounts for up to 3000 contacts. Perfect contacts are required for correct test results. To avoid creating false line defects, there should be no high impedance contacts, nor should the probe card have pin-pin shorts. The probing tester inspects a panel by injecting voltage and current signals into the panel during one cycle. After a holding period, the signals impressed onto the pixels will be read out by an external electric circuit. Additional software is then used to analyze the data to determine the presence of defects.
A major drawback of using a tester based on a probing technique for testing the TFT array is its high running cost, especially when probe cards must be custom-built for each size and type of FPD and replaced frequently. Figure 5 shows the COO model block diagram. Assuming that a testing technique employs a prober for contacting a few thousand pads on each panel, it can also detect all types of defects. However, false defects result from neighboring probe pin shorts, high impedance contacts, or misaligned probes. The probing contact is not very flexible, due to the complexity of aligning several thousand pins.
The fixed and variable cost, C31, for a typical tester employing probing contacts is $1,416,000. Compared to voltage imaging testing, this higher cost is partially due to a much higher consumable cost. Each probe card has a finite lifetime and the cost of a replacement probe card is about $60,000 to $100,000. Approximately one probe card needs a changeover every month. If a probe card can operate 60,000 touchdown cycles and each machine tests about 720,000 panels/year, then 12 probe cards will be cycled, at a cost of about $720,000 to $1,200,000. Specially trained personnel must align the new probe card, and the alignment takes several hours, so machine uptime will be reduced and an additional machine may be needed when the production capacity exceeds the testing capacity.
Figure 5. Probing tester COO model.
The tester yield, Y31, is the same as the TFT fabrication yield, Y1, because it is assumed that the tester can detect all the defects.
Assuming test cells can detect all defect types, the yield is the same as the cell assembly yield:
The "scrap cost" in the cell assembly is thus
Assuming that, for reasons other than defect coverage (such as probe card contact errors), the probing array tester has a 0.5% error of mis-diagnosing good arrays as bad, and 0.25% error of passing bad panels as good, the a3 and b3 error costs are
For example, if Vp is $80, and W is 2,160,000 per year, then C34 is $1.728 million/(percent of a3). Such an unreliable technique is bound to induce heavy costs due to probing errors:
The total annual cost of using probing array testers is then
Suppose the entire TFT-LCD cost is $500. According to the survey , 16% of this is due to the TFT fabrication, so that Vp is $80. Another 30% is due to the cell assembly process, so Vf is $150. Assuming that the TFT yield, Y1, is 80% and the cell assembly yield, Y2, is 80%, we can formulate the following tables for comparison. The number of TFT panels tested will be based upon the voltage imaging tester throughput, which is calculated at 752,760 panels per year for a single machine.
Table 5 assumed that the probing-based test system will have short MTBF and more frequent maintenance, so the machine utilization is lower and an extra test system is required. It is also assumed that the probe cards creates probe pin shorts so that it has higher mis-tests. Combining the above assumptions, voltage imaging testing can save up to $1.5 million/year more than the probing-based systems. Table 6 shows that voltage imaging testing also costs less on every level, and the total is about $5 million less than the probing-based test systems. From Table 7, it can be seen that, by using either voltage imaging testing or a probing-based test system, $60 or $55 million can be saved when compared with cases when no testing is performed.
From the above discussions, the following conclusions can be drawn:
It is necessary to perform testing on panels.
Voltage imaging testing has many technical and economic advantages over a typical probing test system, and it is a more beneficial test system in general.n
Voltage Imaging is a trademarked proprietary technology used in the in-process testing systems (IPT) from Photon Dynamics Inc.
1. Francois Henley, "Voltage Imaging: A New Method to Locate Point and Line Defects," SID `92 Digest.
2. Francois Henley, Ying-Moh Liu, Kazuo Otsuka, "A High Speed Flat Panel In-Process Test System for TFT Array Using Electro-Optic Effects," IEICE Trans. Electron., Vol. E76-C, No.1, Jan. 1993.
3. Ying-Moh Liu, et al., "Modeling and Analyses of Voltage Imaging Spatial Resolution," IS&T/SPIE `94 Elect. Imaging Conf., 1994.
4. Ying-Moh Liu, "Active Array Testing in Mass Production Using Voltage Imaging," Elect. Disp. Forum `95, Yokohama, Japan.
5. Ying-Moh Liu, et al., "Line Open and Short Defect Classification Methodology for AMLCD Array Test Using Voltage Imaging," SID 95 Digest, pp. 591-594.
6. Francois Henley, Ying-Moh Liu, Alan Nolet, "Voltage Imaging for High-Throughput Active Array Test," SEMICON/Kansai, 1995.
7. "Flat Panel Display 1995," ed. Nikkei Microdevices, pp. 76-84.
8. PDI Application Note, "Fundamentals of Voltage Imaging Theory," PDI P/N 008906, Rev. A, 10-20, 1994.
9. David W. Jimenez, Howard Ignatius, "The Application of Cost of Ownership Simulation to Wafer Sort and Final Test," Manuf. Test Conf. 93, pp. 5-13, 1993.
10. Darel L. Dance, "Estimating the Cost of Ownership for Test and Metrology," Manuf. Test Conf. 93, pp. 17-22, 1993.
11. F. J. Henley, R. Mui, D. H. Scott, J. C. Speedy, "Tradeoffs in Panel Designs for Cell Testing," Solid State Technology, Test & Metrology Supplement, pp. S17-S20, Aug. 1995.
12. William C. O`Mara, "AMLCD Manufacturing," SID 1994 Seminar Lecture Notes, pp. M-3/18-38.
YING-MOH LIU received his PhD in optical sciences from the University of Arizona in 1987, his MS in optical engineering from the University of New Mexico in 1983, and his BS in electrophysics from National Chiao-Tung University in 1978. He has an extensive background in optical design engineering, applications engineering, and product marketing. He has been with Photon Dynamics for more than six years
and is currently the engineering project manager for developing new technologies for flat panel display test and repair equipment. He has played a major role in the development and application of Photon Dynamics` Voltage Imaging technology. Photon Dynamics, 6325 San Ignatio Ave., San Jose, CA 95119; ph 408/360-3041, fax 408/226-9910.