We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability. In further response to these challenges, we see logic processes adopting FinFET devices along with read- and write-assist circuits in SRAMs. Emerging memory technologies are making steady progress towards product introductions, including PCRAM and ReRAM, while STT-MRAM is beginning to become a strong candidate for both standalone and embedded applications.
Embedded SRAM continues to be a critical technology enabler for a wide range of applications from high performance computing to mobile applications. The key challenges for SRAM include VCCMIN, leakage and dynamic power reduction while relentlessly following Moore’s law to shrink the area by 2× for every technology generation. As the transistor feature size marches toward sub-30nm, device variation has made it very difficult to shrink the bit cell size at the 2× rate while maintaining or lowering VCCMIN between generations. Starting at 45nm, the introduction of high-k metal-gate technology reduces the Vt mismatch and enables further device scaling by significantly reducing the equivalent oxide thickness. Starting at 22nm and beyond, new transistors such as FinFETs and fully-depleted SOI are key to enabling the continuous scaling of bit cell area and low voltage performance. Design solutions such as read/write assist circuitry have been used to improve SRAM VCCMIN performance starting at 32nm. New SRAM bit cells with more than 6 transistors have also been proposed to minimize operating voltage. For example, 8T register file cells have been reported in recent products requiring low VCCMIN. Dual-rail SRAM design emerges as an effective solution to enable dynamic voltage-frequency scaling (DVFS) by decoupling logic supply rails from SRAM arrays and thus allowing much wider operating window. It is important for SRAM to reduce both leakage and dynamic power, keeping products within the same power envelope at the next technology node. Sleep transistors, fine-grain clock gating and clock-less SRAM designs have been proposed to reduce leakage and dynamic power. Redundancy and ECC protection are also keys to ensure yield and reliability when embedded SRAM products go to production. Figure 1 shows the SRAM bit cell scaling trend on the left axis and the SRAM VDD scaling trend on the right axis, using data from major semiconductor manufacturers.
High-Speed I/O for DRAM
In order to reduce the bandwidth gap between main memory and processor frequencies, external data rates continue to increase as conventional high-speed wired interface schemes such as DDR(x) and GDDR(x) for DRAM evolve (Figure 2). Currently GDDR5 and DDR4 memory I/Os operate around 7Gb/s/pin and 3Gb/s/pin, respectively. To achieve higher speed data transfer rate, signal integrity techniques such as crosstalk, noise and skew cancellation, and speed enhancement techniques such as equalizer and pre-emphasis have been developed. These advanced techniques have pushed I/O speeds towards 10Gb/s/pin. Lower power consumption for data center and mobile applications is also pursued. A near ground signaling method, termination impedance optimization, decision feedback equalizer, and clock-feathering slew rate control technologies have been demonstrated to reduce the power dissipation of memory interfaces significantly, while achieving high bandwidth.
In the past decade significant focus has been put on the emerging memories field to find a possible alternative to floating gate nonvolatile memory (NVM). The emerging NVMs, such as phase-change memory (PRAM), ferroelectric RAM (FeRAM), magnetic spin-torque-transfer RAM (STT-MRAM), and resistive memory (ReRAM), are showing potential to achieve high cycling capability and lower power per bit for both read and write operations. Some commercial applications, such as cellular phones, have recently started to use PRAM, demonstrating that reliability and cost competitiveness in emerging memories is becoming a reality. Fast write speed and low read-access time are being achieved in many of these emerging memories. At ISSCC 2013, a 32Gb ReRAM cross-point array is demonstrated in 24nm technology. Figures 3 and 4 provide a summary on the scaling trends for both bandwidth and density in emerging memories.
NAND Flash Memory
NAND Flash memory continues to advance towards higher density and lower power, resulting in low-cost storage solutions that are enabling the replacement of traditional hard-disk storage with solid-state disks (SSDs). Multiple bits per cell has proven to be effective in increasing the density. Figure 5 shows the observed trend in NAND Flash capacities presented at ISSCC over the past 18 years. With scaling, device variability and error rates increase, requiring system designers to develop sophisticated control algorithms to offset this trend. Some of these are implemented outside the NAND silicon in the system memory controller, especially ECC and data management methods, for improved overall reliability. Possible future scenarios include 3D stacked NAND vertical gates as a solution to further increase the NAND density.
This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.