Demand for ubiquitous mobile functionality to achieve enhanced productivity, a better social-networking experience, and improved multimedia quality, continues to drive innovation in technologies that will deliver to these objectives in an energy and cost-efficient manner. While the performance of embedded processors has increased to meet the rising demands of general-purpose computations, dedicated multimedia accelerators provide dramatic improvements in performance and energy efficiency of specific applications. Energy harvesting is another area of growing importance, leading to technologies that leverage non-volatile logic-based SoC’s for applications that do not have a constant power source or handheld devices with very limited battery capacity.

Technology scaling continues to be exploited to deliver designs capable of operating at lower voltages, resulting in reduced energy per operation, as well as reducing the area required to implement specific functions. Processors unveiled at ISSCC 2013 are built on a variety of technology nodes, with best-in-class results accomplished along the axes of integration, performance/watt and functional integration, as well as a few industry-first implementations. These are demonstrated in various process nodes ranging from 0.13μm down to 28nm bulk, and SOI CMOS technologies.

Emerging medical applications require a significant reduction in the standby power over state-of-the-art commercial processors. This drives the exploration of new leakage-reduction techniques in both logic and on-chip memories, targeting orders of magnitude reduction in leakage currents. Fast wake-up time requirements drive the need for saving and restoring the processor state.

In the late 1990s, a GSM phone contained a simple RISC processor running at 26MHz, supporting a primitive user interface. After a steady increase in clock frequency to roughly 300 MHz in the early 2000s, there has been sudden spurt towards 1 GHz and beyond. Moreover, following trends in laptops and desktops, processor architectures have become much more advanced, and recent smart phones incorporate dual and even quad-core processors, running up to 2GHz frequencies. Battery capacity, mostly driven by the required form factor, as well as thermal limits imply a power budget of roughly 3W for a smartphone. From this budget, also the power amplifier (for cellular communication) and the displays have to be powered. The available power budget for everything digital is in the range of 2W (peak) to 1W (sustained). As a result, energy efficiency has become the main challenge in designing application processors, graphics processors, media processors (video, image, audio), and modems (cellular, WLAN, GPS, Bluetooth). For video and image processing, the trend has been towards dedicated, optimized hardware solutions. Some new areas where dedicated processors are particularly needed include gesture-based user interfaces, and computational imaging, to name a few. For all digital circuits, the limited power budget leads to more fine-grained clock gating, various forms of (adaptive) voltage-frequency scaling, a variety of body-bias schemes, and elaborate power management strategies.

Interestingly, cellular links, wireless LAN, as well as short links consistently show a 10× increase every five years, with no sign of abating. With essentially constant power and thermal budgets, energy efficiency has become a central theme in designing the digital circuits for the involved signal processing. Historically, CMOS feature sizes halve every five years. For a brief period in the 1990s, CMOS scaling (a.k.a. Dennard scaling) provided a 23 (α-3) increase in energy efficiency per five years, almost matching the required 10×. During the past decade; however, CMOS scaling offers a roughly 3× improvement in energy efficiency every five years. The resulting ever-widening gap has led to alternative approaches to improve energy efficiency, namely, new standards, smarter algorithms, more efficient digital signal processors, highly-optimized accelerators, smarter hardware-software partitioning, as well as the power management techniques mentioned above.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.