CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging.
Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond. Among the reasons why are that it offers superior short-channel control and low device variability with undoped channels.
At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.
An electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.
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