Stephen Pateras, product marketing director for Mentor Graphics Silicon Test products, blogs about the new IJTAG standard.
Imagine what the world would be like without standards-based interfaces. Your string of holiday lights might contain bulbs of different size, shape, wattage, and voltage. You wouldn’t be able to Google “standards-based interfaces” from any computer or mobile device. Standards are always established when the real needs of an industry can’t be met by the status quo. This is the case with modern SoC design that incorporates a large amount of intellectual property (IP). The tedious, manual effort involved in integrating and testing IP has come to a breaking point, but a new IEEE standard promises to revolutionize the integration process.
Over the last few years, several of my colleagues have participated in the development of the new IEEE P1687 (“IJTAG”) standard, which brings plug-and-play ease to the integration and testing of IP blocks used in large SoCs. IJTAG, the “I” stands for ‘internal,’ enables any number of IJTAG-compliant IP blocks to be connected in an integrated, hierarchical network with test and control access from a single point.
The IJTAG standard builds on the existing JTAG (IEEE 1149.1) standard for boundary scan and DFT access, and reuses some concepts like the Test Access Port (TAP) and controller. However, unlike with JTAG, which defines a rather rigid and limited access architecture, the networks you can configure with IJTAG are flexible and hierarchical. You can easily add or remove segments in an IJTAG network, so you can configure the IJTAG network based on your particular SoC requirements. You do this by describing your instrument (IP) interfaces and the connectivity between these interfaces using a new language called ICL (Instrument Connectivity Language), and defining the operations to be applied to individual IP blocks using a second new language called PDL (Procedural Description Language), shown in Fig. 1.
Figure 1. Instruments (IP blocks) connected through an IJTAG network to a top level test access point (TAP). Tessent IJTAG automatically retargets the instrument level definitions to the top TAP, enabling control of all IPs from a single access point.
The advantages of IJTAG include the reuse of test and initialization sequences, which is achieved through simple re-processing of the PDL files. This lets you reuse the same test and control information for an instrument from chip-level design to wafer test, package test, board test, system test, yield analysis, and debug. IJTAG can also reduce test and debug times as it supports the ability to activate any number of instruments at the same time. It also allows very efficient access to any subset of instruments due to its highly reconfigurable access architecture.
Lest you think adopting IJTAG will be prohibitively difficult, there is already a software product that provides comprehensive support for the IJTAG standard by automating the integration of test facilities and other instrumentation into complex SoC designs. The solution reads IJTAG files and validates that the components are properly connected to the top-level access point. It then retargets IP-level procedural descriptions to the top-level and translates the results into Verilog test benches and standard test vector formats like WGL, STIL or SVF.
IJTAG was defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three of the largest EDA vendors, and is expected to be rapidly and widely adopted by the semiconductor industry. Replacing ad hoc and custom solutions with plug-and-play automation will be a dream come true for SoC designers and test engineers, saving engineering time and significantly reducing the total length of test sequences for all the IP blocks in an SOC. This translates directly into reduced test time and smaller tester memory requirements.
Stephen Pateras is product marketing director for Mentor Graphics Silicon Test products.