by Paul Feeney, Axus Technology
The International Conference on Planarization/CMP Technology (ICPT) was held Oct 15-17 in Grenoble in southern France. This international event is the world’s largest conference covering chemical mechanical planarization (CMP) and related topics, over a 2.5 day period. Over time, the CMP users groups from around the world that come together to form this event are acting increasingly as one body, and the quality of the information has risen.
ICPT oral and poster presentations can be grouped into a handful of major themes:
- Integration of new device structures, and the CMP processes and slurries needed to support them;
- Advances in equipment and in endpoint and control methods;
- Advanced copper interconnects, and the extension of this to 3D and MEMS technologies;
- Consumables, with a keen focus on mechanistic understanding; and
- Alternative planarization methods and the application of CMP to new materials.
CMP and new device structures
Leading off the discussion of the application of CMP for new devices was a plenary talk by Daniel-Camille Bensahel from CEA-Leti. He stressed the parallel paths that exist today for 14nm technology and beyond between fully depleted silicon-on-insulator (FD-SOI) and multi-gate or FinFET devices. As technology goes beyond these two architectures, the future will lie in making the transition from silicon channels to some combination of germanium, nanowires, and graphene. All of this bolsters the effect we have already seen putting more focus on the use of planarization in creating devices rather than solely in making interconnects.
Invited talks from IMEC and GlobalFoundries nicely covered the complexity of CMP steps now being employed to fabricate leading-edge devices. In years past, shallow trench isolation (STI) CMP was the only set of CMP steps in the front-end-of-line (FEOL) process flow. Now, many new CMP applications are being added and each calls for multiple process steps. The special dielectric fill for FinFET’s creates the need for steps very similar to those used for STI, but drives the need for stopping on the extremely small nitride features that cover the fins. The ILD 0 or pre-metal dielectric or poly-open-polish (POP) CMP that exposes the tops of the dummy silicon for metal gates also has similarities to these two. The metal gate CMP that follows was discussed as being implemented with either aluminum (Al) or tungsten (W) as the bulk material. There was also coverage of techniques similar to those of replacement gates for formation of replacement channel materials made from germanium (Ge), indium phosphide (InP), or indium gallium arsenide (InGaAs).
Papers that delved into a portion of these new CMP applications pointed out some of the unique challenges. Catherine Euvrard from CEA-Leti pointed out that POP CMP must not only retain tight control over remaining film thickness, but must do so while simultaneous removing nitride and oxide materials deposited at slightly different heights due to the non-planarity remaining after STI. Another difficulty is that the pattern removal rates of nitride and oxide do not follow what might be expected from blanket rates on each of the films when polished separately. Patrick Ong from IMEC went into the development of a 2-step process for replacement Ge channels. The epitaxial overgrowth of Ge is polished back to oxide and then buffed to produce roughness in the range of 2Å. Ulrich Kuenzelmann from TU Dresden showed results from their implementation of Al CMP. These papers were all geared towards advanced logic. Hynix also contributed with talks on new ceria particles for lower defectivity in STI and CMP for buried gates or wordlines for advanced memory. For buried wordline CMP, the bulk metal includes W and must stop on a nitride layer.
CMP equipment, materials, and methods
On the second theme of equipment, a variety of new hardware and control options were highlighted. Len Borucki from Araca pointed out the slurry flow reduction or oxide removal rate gain with a “slurry injector” apparatus. A second talk from Araca described similarities and differences seen in doing CMP of 300mm vs. 450mm wafers. Polishing of 450mm wafers can generate temperatures a few °C higher, which is likely to have a noticeable effect on temperature sensitive steps such as Cu CMP. Pusan National University and G&P Technology showed that they were able to achieve a radial non-uniformity (NU) of 3% at 2mm edge exclusion with their wafer carrier that contains an “edge profile ring” between the wafer and the retaining ring.
A number of papers described ideas for metrology. Applied Materials and a few customers covered the application of white light illumination for endpoint control across a range of FEOL CMP applications. Improved results were presented for STI thickness, POP thickness with closed loop control of both profile and polishing time, as well as establishment of endpoint control of a process for replacement SiGe channels. Silvio Del Monaco from STMicroelectronics displayed a technique for in-situ measurement of pad groove depth that could be used in characterizing the pad cutting rate of conditioner disks. Florent Dettoni from CEA-Leti described a technique they developed to stitch together interferometric scans to create accurate maps of topography both for whole dies as well as across wafers. Those results were correlated to profilometer scan data, but measurements can be done much quicker. Chandar Palamadai laid out the process that KLA-Tencor has created for quantification of scratching through analysis of blanket wafer haze maps.
CMP and Cu interconnects
The next major theme regarding copper (Cu) included advanced interconnects both for wafers as well as quite a bit on 3D interconnects. Olivier Robin from STMicroelectronics taught us how sheet resistance control mean and variation can be improved by switching to a barrier process with higher selectivity between the dual hardmask and the dense ultralow-k material just below them. Jie Lin from Fujimi described work to develop a slurry for Cu that can get good planarization efficiency despite being used with a pad of moderate hardness. Contributors from Fudan University and from DuPont covered work studying the corrosion and removal rate behavior of the cobalt and molybdenum materials being investigated as part of new barrier material stacks.
ICPT has given increased attention to 3D interconnects and the formation of through-silicon-vias (TSVs) over the last few years. This year included an overview by Viorel Balan from CEA-Leti of some of the issues that need to be addressed in order to do Cu-to-Cu direct bonding. A key to success was identifying and improving topography across several length scales. Both he and Benjamin Steible from ISIT gave evidence that new generations of abrasive-free slurries provide a nice advantage in controlling the dishing of especially larger structures. Jinhai Xu talked about his work at SMIC demonstrating that rings of corrosion at the edges of vias can be seen as a recessed area when there is still about a micron of bulk copper left on the wafer. Rob Rhoades showed two different processes for the TSV nail expose process depending on whether it is an active wafer or an interposer. Catharina Rudolph from Fraunhofer presented a story showing that the combination of high-density TSVs and a higher-temperature anneal actually leads to enough stress that the wafer can explode.
Over time, consumables for CMP have become more specialized to fit the needs of individual process steps for each application. Consumable topics have always been a popular topic at ICPT and this year was no exception. In the area of pad conditioning, there were two topics that received the most attention. One was applying conditioning techniques to the double-sided polishers used in wafer polishing. Jorn Kanzow from Peter Wolters reported that conditioning provided edge control for the double-sided polishing that is now necessary for achieving flatness for 300mm wafers. The second was the study of pad debris that is generated during pad conditioning and how it leads to an increase in scratch defects. Scratching was shown to be best when doing excitu conditioning or when vacuuming the debris off the pad. A relatively recent style of conditioner uses diamond coating over an engineered surface. 3M presented a summary of their efforts to do that utilizing some of their micro-replication methods.
Keiichi Kimura from Kyushu Institute of Technology presented some very exciting concepts surrounding research done to identify individual removal events during CMP. Through the use of evanescent light, where laser light is bounced off a prism surface, individual slurry particles that come in contact with the prism are illuminated. Their findings put forth the idea that pad asperities and the fluid around them cause adhered particles to be pulled off the polished surface. This happens at velocities much slower than what the pad achieves across the wafer -- which rebukes a standard theory that removal is from 3-body contact of a pad asperity pushing a slurry particle into the film being polished. Greg Gaudet from Cabot Microelectronics provided an argument for removal rate with softer pads being driven more by the number of contact points between the pad and wafer rather than the total area of contact. This data seems to back up the concepts presented by Kimura.
For slurries, Intel together with Bradley University and MIT had a few talks outlining the outcome of fundamental studies. Alex Tregub made the point that the characterization of particle size is often overly simplified into a mono-modal distribution. Those tests also often use highly diluted slurry that may not be behaving as it would in its normal state. Mansour Moinpour went over results showing how desorption of additives from particle surfaces can be characterized. Joy Johnson from MIT reviewed a collection of literature surrounding particle agglomeration and added some work showing the role additives can play in agglomerate formation. Along somewhat similar lines, Pall got together with Lewis University to characterize the interaction that slurry particles have with the fibers inside of slurry filters, which may lead someday to the use of novel fibers.
New and improved CMP materials, processes
The remaining major theme is the extension of CMP to new materials and other types of removal processes besides CMP that are also being improved upon. Talks covered new materials such as carbon nanotubes with titanium (Ti) for vias, potassium dihydrogen phosphate (KDP) crystals for optics, GST for phase change memory, SiC for hardmask removal, and Ti and Ti02 for biomedical applications. It turns out that lowering surface roughness of Ti02 improves the biocompatibility of surgically implanted materials.
Though there does not appear to be any technology that is threatening the continued adoption of CMP for many applications, there are also other types of processes that have their place. Hyuk-Min Kim from Hanyang University taught us how lapping results could be improved by switching to a fixed abrasive system. Chuljin Park from KIIT showed a multistep process where diamond mechanical polishing was useful followed by CMP for sapphire substrates. Paul Feeney from Axus Technology demonstrated that improvements in grinding technology can make the CMP of Si after grinding much easier and produce better results. Grinding of Si can be done two-orders-of-magnitude faster than CMP and with within wafer non-uniformity unheard of in CMP. Adding CMP afterwards then produces the best possible surface.
Overall, the technical content of this event was very good. Clearly a lot of energy is being applied around the world to make advances on a wide variety of planarization applications. A high bar has been set for next year’s ICPT in Taiwan!
Paul Feeney (PFeeney@AxusTech.com) is director of process technology at polishing and thinning company Axus Technology. He started his involvement in CMP at IBM in 1989, holding both process and equipment responsibilities there, including doing pioneering module process and integration work on copper and barrier CMP for the world’s first commercial copper chips. He spent many years at Cabot Microelectronics; as a CMP Fellow there, he led development of a wide range of materials for leading-edge CMP applications. He is also a co-leader for planarization topics for the ITRS.