July 12, 2012 -- Day 2 of Semicon West 2012 began a bit earlier than usual with the Sokudo Lithography Breakfast Forum, which focused on directed self-assembly (DSA). The first question was anticipated by Atsushi Yasue, emcee and CTO of Sokudo, who opened his remarks with “Is DSA just an interesting science project?” Given that Sokudo is introducing its Duo dual track product for DSA, I suspect he believes it is more than that.
Michael Garner, chairman of the ITRS emerging nanotechnology group, opened the technical sessions with the ITRS view of DSA. DSA was first identified as a potential lithography extension in 2007; in 2011, SPIE conferences included several presentations on evidence of DSA defect reduction. Progress has been made, though defects are still unacceptable at the 100ppm level. A brainstorming session at SPIE 2012 recommended specific topics for university and consortium pre-competitive research activity.
Yoshi Hishiro of JSR Micro has been working on DSA polymer blends and applications for several years already, both block copolymers and polymer blend systems. One specific application is contact hold shrink, which includes one method that can be used in combination with EUV. Contact hole repair, making features uniform and round, is another activity with strong customer pull. A patterning doubling method allows extension of a rectilinear grid of contact holes to a staggered grid with twice the density. Clearly, design objectives are constrained to a menu of what DSA is capable of delivering.
Serge Tedesco of CEA Leti described the IDeAL program at Leti, opening his presentation that included the characterization of DSA for microelectronics using block copolymers as an “easy process” with “low cost.” The number of SPIE DSA papers grew from 5 to 25 to 55 in 2010-2011-2012. The Leti 300mm pilot line has demonstrated 100nm contact hole shrink to 15nm, but CD and defect metrology is a challenge. He believes DSA could be inserted as a complementary lithography technique as early as the 14nm node.
Steve Renwick of the Imaging Solutions Technology Development group at Nikon gave a hardware perspective on DSA with 193nm immersion lithography. From his world view, these DSA materials actually want to do what we want them to do, irrespective of the hardware optics. Rather than a competitor, DSA is a high potential complement to 193i litho. Demonstrations have been executed showing that DSA is capable of healing print defects in the pattern, because DSA wants to form the target structures. Because of the commercial implementation of double patterning, litho tools are already capable of meeting the overlay requirements of 2-3 nm required for some DSA applications. Given the successes already demonstrated, he believes DSA will indeed fly as a complement to 193i.
Charles Pieczulewski of Sokudo spoke on the path to defect free manufacturing with DSA. Pilot development activity began five years ago on the existing RF3 track, and has evolved to the new Duo track that is designed specifically for DSA. Development studies included work to determine the pre-pattern CD range that was required to reduce the DSA defect density, those defects ranging from single dislocations to gross pattern randomization. One study on defect characterization for a contact hole shrink application encompassed 550,000,000 vias; this is why we have graduate students. They found 22 missing vias, 8 due to particle contamination and only 14 due to poor DSA phase separation. The student’s leopard hallucinations are subsiding. Additional DSA tracks will move into pilot production now through 2013, with HVM tools to start shipping in 2014.
Linda He Yi of Stanford U (student of H.-S. Phillip Wong) opened her remarks with the observation that long-range order is not required for chip manufacturing. Rather, the objective can be altered to place specific patterns in specific locations of limited area. One can create a template for each individual feature to be created with DSA; or in this approach, multiple DSA features can be fabricated with a library of templates that can be used repeatedly to generate, in effect, ‘random’ design features. The benefit of such a library is a relaxation of resolution requirements for the template patterning. Once again, DSA is found to heal defects in the litho patterns. By the way, Linda is the lucky grad student who got to inspect the 550,000,000 vias cited above.
The NCCAVS CMPUG staged its 5th annual meeting concurrent with Semicon West, this year returning to a separate room rather than being held on the show floor where the seats are too few and the decibels are too many. As always, the CMPUG presentations will be posted on the NCCAVS CMPUG website in the coming week or so.
The first speaker was yours truly, Michael Fury of the Techcet Group, providing the annual CMP consumables market update. Pad & Slurry revenues are up 3% over 2010, with a 2012 forecast up 5.7% to $1.73B. Combined with pad conditioners, PCMP cleaners, PVA brushes and slurry filters, the CMP consumables business achieved a $2.04B milestone in 2011.
Iqbal Ali of SEMATECH @ Albany updated us on the status of CMP’s role in 3D TSV activities there. The TSV story remains primarily a copper CMP market from this group’s perspective, but the demands for removal rate of thick copper, planarity of large features (compared to on-chip interconnects), and selectivity to different materials demands unique CMP products and processes if TSV is to be successful in HVM. SEMATECH has been working with Cabot Micro and Air Products to develop a working backside reveal process for copper CMP and alkaline post-clean (CP98-D) that keeps cross-contamination of the exposed silicon under control, as quantified by the Qcept ChemetriQ tool.
Paul Feeney of Axus Technology took us back to the future with a discussion of polishing non-uniformity, beginning with the use of multi-wafer templates by the Cro-Magnon. Polishing heads are currently being designed with 8 zone control and ≤2mm edge exclusion. Migration to 450mm will exacerbate the center-to-edge depletion of slurry reactants and the temperature differential between the wafer leading and trailing edge, which drives reaction kinetics. The 54nm Cu line widths scheduled for production in 2013 will struggle with Cu losses due to the combined effects of non-uniformity, imperfect selectivity, and edge roll-off. Polishing head upgrades for 200mm and even 150mm wafer polishers are still in demand by smaller fabs and research labs for achieving state-of-the-art performance on retro platforms. You know, the kind found in cave drawings.
Mike Corbett of Linx Consulting talked about the impact of the now-inevitable 450mm conversion on CMP consumables. CMOS wafer starts drive the CMP market, and this segment is lagging the overall chip market. The Linx slurry & pad market estimate is $1.615B for 2011. The supplier consolidation index used by the US Department of Justice indicates that confirms the expectation that tungsten slurry is highly consolidated, though not to the extent of monopoly, while the other slurry segments are well diversified with a balance between suppliers from the US and Japan. Fab projections foretell a peak in 300mm wafer production in 2021, with 450mm starting to scale to high volume production in 2018. By 2025, the MSI (millions of square inches) of silicon processed in 450mm will cross over and exceed the 300mm production. Slurry & pad costs are projected to increase 35-50% per wafer, depending on the actual increase in slurry flow rate (used 1.2x to 1.5x) needed to achieve process specs.
Michael Fury, speaking this time as Vantage Technology, presented several tales from the sub-fab, describing the kinds of anomalies that have been observed in customer slurry distribution lines around the world using the continuous monitoring capability of the SlurryScope. Monitoring large particle counts for post-mortem diagnosis of wafer scratching incidents is useful for understanding and for future-looking corrective actions, but that is only part of the story. Monitoring particle behavior continuously teaches the patterns of drifts and spikes in the slurry supply, making it possible to learn the special causes associated with each type of behavior observed, eliminate those causes, and actually prevent slurry-induced scratching incidents with stable line performance.
Bruce Kellerman of MEMC talked about the 450mm transition from the wafer manufacturers’ point of view. The arguments supporting the 450mm transition parallel those for the 300mm transition, though the number of players that are both able and willing to afford it is dwindling. Siltronic, Sumco and MEMC have all announced workforce and facility reductions in the past 8 months. From over 20 wafer producers at 150mm, we are down to 6 suppliers at 300mm; Bruce used “?” for the count at 450mm, but all presently have active 450mm programs in place. That doesn’t mean all will remain viable, especially given the small number of fab customers. Intel, Samsung and TSMC are pretty much guaranteed customers, but even they have divergent specs. To get costs in line, a greater degree of standardization across fab customers is required.
While I do appreciate the relative quiet and sanity of holding this CMPUG meeting in a separate room away from the show floor, I realize now that the penalty we paid is that we had no access to the Happy Hour that started on the show floor two hours before we concluded our business. When people talk about CMP placing unreasonable demands on people, this is what they’re talking about.
Michael A. Fury is director and senior technology analyst, Techcet Group and a regular contributor to Solid State Technology. Read his reports from the Gartner/SEMI forecast meetings, and from CEA-Leti's research presentations.