July 12, 2012 -- CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.
Also read: Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti by blogger Michael A. Fury, PhD.
Check out the videos for details on the research:
Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.
Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.
Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.
Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.
What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it -- preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.
Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.