July 12, 2012 -- There’s no doubt that fabless semiconductor companies are taking a keen interest in the semiconductor manufacturing supply chain and processes. To that end, SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.

Check out insights on the Day 1 keynote from Intel here.

There’s nothing new about the goals of semiconductor designers and manufacturers, Bolsens said, sharing some decade-old slides to make his point. Power density, Moore’s Law, and lowering costs have always been important, and innovation in technology and business models has always generated solutions.

The fabless semiconductor company’s goal is to add value to the system-level design. To do this, Xilinx has taken the approach of device flexibility, paired with 3D interconnection for higher performance/lower power/higher reliability. Bolsens notes that the company is collaborating much earlier with the supply chain and in a much broader fashion than ever before to achieve these goals.

Programmable chips offer flexibility, even while they may appear to have a higher cost than dedicated products. The ability to customize a chip for your functions, and use the same chip across various system-level configurations, leads to costs savings, Bolsens said, referring to time savings as a direct benefit. Logic can also be tuned to accelerate some functions, boosting performance. To save energy, FPGAs offer “fine-grain” programmability.

On the 3D and 2.5D packaging front, Bolsens shared the benefits of using multiple smaller die integrated in one package. Interconnect innovations increase the bandwidth/Watt consumed, and chip yields go up compared to fabricating one large die. When small FPGA die replace a large monolithic die, designers can use “best of breed” die for different functions. Isolation of different blocks also improves.

3D integration and other technology answers for the semiconductor industry’s challenges are in place, summarized Bolsens. Now, the supply chain must build up around them, with supporting information like process development kits (PDKs), design for manufacturing (DFM) rules, and other standardization efforts.

Bolsens recommends creating a continuous supply chain feedback loop while in the early ramp-up of a product, harkening back to his earlier points about collaborating early and often with the ecosystem that will enable your chip to reach market.

Check out Ivo Bolsens' biography here, courtesy of SEMI.

Check out Solid State Technology’s coverage of SEMICON West 2012!