June 5, 2012 -- Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on-chip communication. That was one of the conclusions put forth by imec’s An Steegen, speaking on technology trends at The ConFab 2012. Steegen is Senior Vice President Process Technology Development at imec, where she has the responsibility for the technical leadership and execution of IMEC’s CORE Program activities in the areas of devices, process, lithography and design and CMORE activities such as MEMS, Power, Sensors and Photonics. 

She began by outlining the requirements for future applications, noting that, at a very high level, people want everything. “You want high speed, you want to increase battery lifetime, more data storage, multi-functionality, all at a reduced cost,” she said. “You also want heterogeneous integration, and of course, it all needs to fit into a handheld device.”

She said designers today are using a lot of techniques such as parallelism and dynamic voltage switching to work within a battery lifetime constraint. “The challenge here is going to be the active leakage current. What this means for your future technology is that you basically have to put leakage as a constraint, which will automatically pin the performance,” Steegen said. She noted that this constraint is only for mobile devices, and isn’t a problem for wired devices such as servers. This means CMOS development will evolve in two directions, one for wireless and the other for wired.

Steegen said technology scaling is the key, and that’s still driven by Moore’s Law, which dictates that the number of transistors in an integrated circuit has to double every two years to offset the ever increasing R&D cost. “The technology knobs for system scaling are the famous four: power, performance, area and cost (PPAC),” she said.  

Area is still very much lithography enabled, Steegen noted, presenting a chart showing the key dimensions of a transistor from 28nm technology down to a 10nm CMOS -- the three key dimensions are the gate pitch, CPP, the metal 1 pitch and the finFET pitch. “What you need to scale the area for each technology from generation to generation is 50%, so each of these key dimensions will have to shrink by 0.7X. If today at 28nm, your gate pitch is 110nm, we will push that down to 40nm in the 10nm node. Another one to remember is the 42nm finFET pitch,” Steegen explained.

It’s not only the dimensions of the transistor that have been pushed over the last decade, it’s also the overlay, the layer-to-layer accuracy in device patterning. “If you look at the trends here, when the industry was working with 1 micron technology, a 300nm overlay spec was still doable. When you go into the more advanced nodes like 20nm, 5nm overlay is definitely what you need if not less,” she said.

In another graphic, she focused the audience’s attention on the red line, the logic scaling line, and need need for 43nm finFETs. That equates to a half pitch of 20-22nm. “That means you’re in this dark gray box which basically tells you which tool is going to be needed to print this technology. You’re clearly already in the area of EUV. If you don’t use EUV here, you come automatically back to the 193nm immersion tools where you multi patterning to print the layers for these technologies.”

Steegen said one of the key challenges we’re facing right now is EUV tool readiness for the 14nm node. “A lot of effort is being spent right now on EUV readiness and on the source power readiness,” she said. Showing a photo of ASML’s 3100 EUV pre-production tool at imec, she said “That tool is able to do great things. We were able to print 16nm half-pitch lines and spaces with a single exposure. Also, the overlay ability of this tool is very promising, with 3 sigma overlay specs below 2nm.”