JEDEC publishes LPDDR3 standard for low-power memory chips

05/17/2012

May 17, 2012 -- JEDEC Solid State Technology Association, standards development association for the microelectronics industry, published the JESD209-3 LPDDR3 Low Power Memory Device Standard, targeting the performance and memory density demands of new-generation mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on high-speed 4G networks.

“To help address the dramatic rise in data-intensive apps and the resulting demands on device memory, JEDEC LPDDR3 is designed to focus on higher bandwidth requirements for device processors and graphic units,” said Hung Vuong, chairman of JC-42.6.

Also read: JEDEC publishes wide-I/O mobile DRAM standard

LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over LPDDR2. LPDDR3 achieves a data rate of 1600Mbps (LPDDR2 achieves 1066Mbps) through write-leveling and CA training, on-die termination (ODT), and low-I/O capacitance. LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management. As with LPDDR2, LPDDR3 supports both package-on-package (PoP) and discrete packaging types to meet form factor requirements of various mobile devices.

Write-leveling and CA training allow the memory controller to compensate for signal skew, ensuring that data input setup and hold timing as well as command and address input timing requirements are met while operating at the fastest input bus speeds.

ODT enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count.

Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC website: http://www.jedec.org/sites/default/files/docs/JESD209-3.pdf.

Also read: Samsung claims industry-first LPDDR3 30nm DRAM

JEDEC develops standards for the microelectronics industry. For more information, visit www.jedec.org.

Visit the Semiconductors Channel of Solid State Technology!

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. 


VIDEOS

Electroiq 2 EIQ2

TECHNOLOGY PAPERS

Automated Test Creation for Mixed Signal IP using IJTAG

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis

This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...

WEBCASTS

Innovation in Semiconductor Manufacturing Instrumentation

As the industry is incorporating more MEMS devices with integrated magnetic sensors, they are encountering challenges that cannot be overcome with ...

3D and 2.5D Integration: A Status Report Live Event

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

Oh, snap!: Pics from The ConFab

Sun Jun 03 19:09:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

Volume 56, Issue 1

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS