May 17, 2012 -- JEDEC Solid State Technology Association, standards development association for the microelectronics industry, published the JESD209-3 LPDDR3 Low Power Memory Device Standard, targeting the performance and memory density demands of new-generation mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on high-speed 4G networks.
“To help address the dramatic rise in data-intensive apps and the resulting demands on device memory, JEDEC LPDDR3 is designed to focus on higher bandwidth requirements for device processors and graphic units,” said Hung Vuong, chairman of JC-42.6.
LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over LPDDR2. LPDDR3 achieves a data rate of 1600Mbps (LPDDR2 achieves 1066Mbps) through write-leveling and CA training, on-die termination (ODT), and low-I/O capacitance. LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management. As with LPDDR2, LPDDR3 supports both package-on-package (PoP) and discrete packaging types to meet form factor requirements of various mobile devices.
Write-leveling and CA training allow the memory controller to compensate for signal skew, ensuring that data input setup and hold timing as well as command and address input timing requirements are met while operating at the fastest input bus speeds.
ODT enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count.
Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC website: http://www.jedec.org/sites/default/files/docs/JESD209-3.pdf.
JEDEC develops standards for the microelectronics industry. For more information, visit www.jedec.org.