Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.
Day 3 of the MRS Spring 2012 meeting opened Wednesday at Moscone West in San Francisco under partly sunny skies after an air-cleansing pre-dawn sprinkle. The halls were much more quiet and subdued than yesterday morning, suggesting a busy Tuesday night for all of the science bars in town.
C3.1 TM Shaw of IBM Watson Research opened the day with a reliability talk on leakage and TDDB in low-κ dielectrics. Leakage was measured with comb structures (60-100nm spaces) using step-wise voltage ramps; data recording started one minute after each step to eliminate charging transients. Over time, the Poole-Frenkel barrier height decreases continuously. At longer test times (>200 hours) the leakage data is more indicative of tunneling between trap sites; overlapping trap sites provide the leakage path. The rate of decrease of the Poole-Frenkel barrier height in early life testing was found to correlate well with TDDB behavior in longer time testing, and may serve as an early screening proxy. Both moisture and Cu ions have a significant impact on time dependent leakage, but the magnitude of the leakage currents does not correlate well with TDDB lifetime.
C3.2 Sean King of Intel PTD studied the band diagram of the low-κ/Cu system with XPS and REELS to elucidate some fundamental understanding of interconnect leakage mechanisms. He focused on the interface between Cu, the SiCON:H low-κ etch stop and the SiOC:H. Leakage through the etch stop was shown to dominate over direct via-to-via leakage through the Ta barrier and the dielectric. Future work will expand on the defect trapping states in this materials system. The talk concluded with an announcement that resumes of new graduates are welcome, as Intel needs to staff a new R&D facility currently under construction in Oregon.
C3.3 Brad Bittel of Penn State described some magnetic resonance studies of BEOL dielectrics; this work is a collaboration with Intel’s Sean King (above). Defects observed with EPR are likely important to leakage current as well as related reliability phenomena. SDT provides a direct link between EPR defects and electrical transport because only the centers involved in leakage can show up in SDT.
K3.5 Daniel Steingart of City College NY told us about flexible storage and energy conversion. Their approach was to focus on making the binders and electrodes flexible by embedding the MnO2 and Zn electrodes in a Ag-impregnated nylon mesh (this is the work I reported on earlier this week). This battery represents a conventional material set, but the Zn/MnO2 couple degrades over time as its charge/discharge cycles drive it to a stable equilibrium that is not a useful energy source. The limit seems to be ~600 cycles. Efforts to develop alternate material systems found adhesion failure between Al electrodes and a polymer/nanoparticle composite electrolyte in early test capacitors. It was resolved by using a seed layer of the nanoparticle alone as a surface roughening treatment to promote adhesion of the composite.
C4.1 Roy Gordon of Harvard U spoke on Mn capping layers and diffusion barriers in copper interconnects for TSV and on-chip vias, including a unique void-free via fill process. The Mn CVD precursor for capping is a metal amidinate that deposits at 300°-350°C at 5 torr selectively on the Cu surface after passivating the dielectric with BDDS or DTS. Mn is a fast diffuser in Cu that migrates to SiO2 and Si3N4 interfaces, leaving the Cu resistivity after 400°C anneal at the pre-Mn level. Adhesion strength to the dielectric increases with Mn at the interface. An 8nm MnSixOy layer was shown to prevent both oxygen and moisture diffusion into the copper. Iodine-catalyzed copper bottom-up fill requires a copper seed layer before the mechanism can initiate. This work found that a seed layer of CVD Mn4N (Mn amidinate with NH3 at 130°C) will also adsorb the iodine sub-monolayer to initiate the CVD Cu fill at 180°C. Seam-free Cu fill was shown for <20nm vias with 5:1 AR, with large Cu grains across the entire via diameter prior to anneal. The Cu resistivity is lower than EP Cu due to the greater purity of CVD Cu. TSV copper fill was also demonstrated with AR>25:1 and 460mΩ/square Cu which exceeds the current roadmap.
C5.1 George Antonelli of Novellus provided some insights into the ideal hard mask for copper interconnects at 20nm and below. Carbon films are deposited at 275°C with ion bombardment, yielding the same density as conventional films deposited at 500°C. Surface roughness was RMS 0.5-1.1nm, which impacts line edge roughness (LER). Line bending with this system was tested over the range AR 3.2 to 5.7 and was found to peak at AR 4.5 rather than increasing monotonically as AR increases. This was due to the interplay of mechanical stress with other process parameters and material properties. A doped SiC material was designed as an alternative to TiN hard mask to facilitate chemical removal or CMP after etch. More recently, work is underway on an undoped carbide variant that can be removed with wet etch and does not require CMP.
N7.1 Sang-Woo Kim from Sungkyunkwan U (Korea) described a high performance, transparent, flexible, stretchable, foldable (whew!!) nanogenerator based on multi-dimensional ZnO structures. Harvesting electrical energy from mechanical motion and vibration is the common objective, but the scope can range from replacing pacemaker batteries (not recommended for avowed couch potatoes) to embedding large area arrays in roadbeds to use traffic to generate power. PVDF is a material of choice for generating high output voltage, while ZnO is preferred for generating high output current. Graphene sheets were transfer printed onto a PEN polymer substrate, and ZnO vertical nanorods (1D) were grown on the graphene. The material functioned well, but the PEN distorted above 250°C. For such harsh conditions, a cellulose paper with Au seed layer was substituted for the PEN, and performed well even under harsh conditions. A 2D alternative was fabricated using ZnO nanosheets aligned vertically between electrodes. The work function of the top electrode limits the current output, with Au > graphene > ITO > Al.
C5.4 Ed Cooney of IBM talked about the stress effects in Cu inductors for RF technologies. While many of us are focused on 20nm and below, these devices still operate in the 0.18-0.35µm regime and require copper layers >3µm thick for proper inductor performance. At these feature sizes, reliability failure mechanisms are driven more by CTE mismatches. Raising the post-plating anneal temperature from 100°C to 250°C reduced the room temperature tensile stress in the Cu which in turn reduces the driving force for delamination of the Cu from the SiN cap layer.
K4.5 Gregory Whiting of PARC showed a viable path toward high volume printing of flexible temperature sensors sensitive to 0.1°C up to 50°C. InSn/V2O5 was the eutectic mixture chosen for this work, with the ink scaled up to 1kg batches. Devices are printed on PET with screen printed Ag electrodes with gap widths varying from 250 to 500µm. The device shows a sensitivity of 1% change in resistance per degree between 20°C and 70°C, though a sensitivity to moisture dictates the needs for encapsulation for field use.
B2.1 Toshiki Hirano of Hitachi Global Storage (now Western Digital) gave an overview of MEMS and NEMS technology applications in the HDD world. HDD recording density has increased 3×108 times since the first IBM RAMAC in 1957. The track width on a 95mm disk today is 68nm (about the same as a human hair in a baseball field), with 3nm clearance between the R/W head and the disk surface. The next generation of actuator may be a moving magnetic element, now in R&D, in place of the moving slider. Another variation is a R/W head with heating elements on either side of the active area. Precise positioning is achieved by thermal expansion of the heater element on either side. Similarly, head height control can be positioned vertically with a resistance heating element, allowing a fly height of 1-3nm in combination with a contact sensor feedback loop. Bit patterned recording disk media are extendible to 10 Tbit/in2 using a self assembled polymer to guide the definition of individual domains. Thermal assisted recording can be facilitated with a near field transducer that has a spot size of 50nm.
N7.6 Rusen Yang of U Minnesota described energy harvesting with ZnO nanowires. ZnO nanostructures are unique in that they have been fabricated into nanobelts, nanosprings, nanorings, nanohelixes, and nanotubes, but nanowires are the focus here. These transducers are adequate to power pH and UV sensors, and the power can be stored to power LEDs. Power delivery is still in the µW to mW range. While the piezoelectric properties of ZnO are of primary interest here, it has other important and useful properties such as biocompatibility that add to its attractiveness for further research.
C6.3 John Zhang of ST Micro talked about the challenges in Cu CMP at 20nm and below. Center-to-edge uniformity is affected by the radial change in via sidewall angle, which gives a larger via top diameter at the edge and therefore a non-uniform tendency for dishing. In shrinking from 1µm L/S to 32nm L/S, Cu dendrites become increasingly problematic but can be controlled with PCMP chemistry. Validation must be established by looking for long term dendrite growth >100 hours after processing, and its effects can show up in TDDB data. The process window is shrinking as uniformity and defectivity often have competing optimization schemes. It was suggested that uniformity and defectivity parameters may have a minimum constant value, but no Heisenberg CMP uncertainty principle was actually articulated.
C6.4 Jae-Young Bae of Hanyang U (Korea) described the correlation of pad conditioning and pad surface roughness with CMP step height reduction, leading to a new slurry concept for initial step height reduction. Picolinic acid was added to ceria slurry; the maximum amount adsorbed on the pad surface for monolayer coverage was 0.36mg/m2. The acid increased the adhesion strength of the ceria particles to the pad surface by ~3x, leading to a 5x increase in removal rate, and 3x increase in planarization rate (60s vs. 180s).
C6.5 Bahar Basim of Ozyegin U (Turkey) talked about a wafer level CMP model to predict the impact of pad conditioning on process performance. Higher wafer scratch levels are correlated with points on the pad at which the conditioner sweep changes direction. Sweeping the conditioner over the edge of the pad surface also creates additional wear when the conditioner transits back onto the pad. The resulting pad profile model enables tailoring the wafer surface to best match the incoming wafer profile.
Also see Mike Fury's other reports from MRS Spring 2012: