Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the second day: OLED TFT displays, single transistor DRAMs, silicon photonic wires, CNTs, 3D optical interconnects, graphene for RF and sensing, transparent ZnO, epidermal electronic systems, stretchable electronics, ultra-low-k dielectrics, patterning of electroceramics, PRAM (an alternative to NRAM), and inkjet printing of superconducting films.
Day 2 of the MRS Spring 2012 meeting opened Tuesday in Moscone West in San Francisco under overcast skies and a light drizzle. The halls were packed at 8am as so many of the symposia lead off with presentations that have high audience appeal.
K1.1 Kazumasa Nomoto of Sony offered Sony’s outlook for the future of ultra flexible AM-OLED TFT displays, enough so to merit the labels foldable and rollable. In a full color 4.1 inch 121 ppi FWQVGA format, an 80µm thick AM-OLED display has a bending radius of 4mm. In a 13.3 inch 150 dpi UXGA format, a 120µm thick electrophoretic display (EPD) has a bending radius of 5mm. This is facilitated by integrating flexible OTFT gate driver circuitry into the backplane. The 20nm thick PXX gate oxide consists of alternative self-assembled layers. Both screen printing and inkjet printing techniques are employed in the process flow.
E1.1 Sorin Cristoloveanu of IMEP-LAHC Minatec guided us along the path to single transistor DRAM (1-T DRAM) in which the capacitor storage cell scales proportionally to the drive transistor. Metastable dip (MSD) DRAM is a hysteresis device that has no associated capacitor. Another variation is ARAM. Below a storage channel width of 10nm, it is not longer possible to sustain a separation of holes and electrons. Inserting a 3nm separator between the two sides of the channel (suggesting a squared off “A”) makes it possible to reduce the total width below 10nm. A new device called Z2-FET is a PIN junction with zero subthreshold swing and zero impact ionization. The fabrication process is compatible with SOI CMOS. URAM is the combination of a 1-T DRAM with a non-volatile memory (NVM) element. Several additional concepts were presented more rapidly than I could keep up.
L1.1 Siegfried Janz of NRC Canada talked about the use of silicon photonic wires as optical sensor elements. Folded waveguides can be configured in dense spirals or grids to achieve, for example, a 2mm long sensing element in a 150µm2 area. These elements can be applied to photonic wire evanescent field (PWEF) affinity binding sensors for DNA, protein and bacteria analysis to 200 pico molar sensitivity. The entire waveguide detector system is fabricated in an oxide layer 200nm thick. Microfluidic channels 200µm wide are aligned and pressed over the PWEF array to flow analyte over the sensor elements. The PWEF sensor arrays are manufactured with 500 chips per wafer in the CMOS foundry at LETI.
J3.1 Rahul Sen of Nantero described the use of CNT formulations in electronic devices. Materials are 300mm CMOS compatible spin coated films that can be lithographically patterned with conventional oxygen plasma techniques. Facilities fabricating with these films include ON Semi and SVTC. The CNT solution has <25ppb metal impurities; the final film has <1×1011 atoms/cm2 for BEOL compatibility. Sporadically high calcium levels >30ppb was resolved with an ion exchange process. One application of this material is the development of an NRAM™ universal memory device using CNT as the switching element.
M1.6 Soenke Steenhusen of Fraunhofer ISC took us from research to reality as regards 3D optical interconnects. The energy required to operate processers suggests a limit of 1.25 TFLOPS/chip which translates to an energy threshold of 6 GFLOPS/watt using conventional metal interconnects. This becomes the fundamental driver for integrating optical interconnects in their stead. The optical waveguide fabrication methodology described involved 2 photon polymerization (2PP) of polymer materials using femtosecond laser pulses.
DD5.2 Tomás Palacios of MIT presented the use of graphene for RF and sensing devices. His approach is to fabricate graphene devices on top of completed CMOS structures, or to make the graphene devices directly on flexible substrates. He uses the PMMA transfer method for graphene grown at 1000°C from CH4 on Cu. His applications of interest cover the whole range of known markets that have been discussed elsewhere. For on-chip interconnects in the range of 100nm wide down to 1nm wide, graphene has a low constant resistivity; in this range, the resistivity of copper spikes exponentially. By fabricating a top-gated GFET on an insulating substrate rather than conductive silicon, the GFET device can exhibit a high fT >20GHz in which the parasitic capacitance is low, meaning that the de-embedded fT is quite comparable to the non-de-embedded value.
BB1.11 Chia-Lin Chuang of National Taiwan U discussed a highly transparent p-ZnO prepared from a non-toxic sol gel. Generally, p-type ZnO is difficult to fabricate for a variety of reasons including native donor defects, deep acceptor levels and unintentional hydrogen doping. Their non-toxic composition included zinc acetate, indium nitrate, IPA, MEA and ammonium acetate. The resulting films have a resistivity of 4.43 Ω∙cm with a carrier concentration of 1.36×1018/cm3.
K2.1 Nanshu Lu (now at UT Austin) of the John Rogers group at U Illinois Urbana presented the groups’ recent achievements in epidermal electronic systems. Micro-transfer printing is the method of choice for interconnecting small rigid silicon electronics elements with thin nanoribbons of silicon or metal. Depositing onto a pre-stretched elastomer substrate provides a resting state in which the interconnects are buckled or canted and can endure up to 100% elongation while imparting ≤1% stress to the rigid circuit elements. The trick of fabricating extremely thin silicon for flexibility applies to the PDMS polymer substrate as well when the objective is to apply the device to the skin and tolerate stretching and bending without adhesion loss. The thin polymer stability is maintained until it is applied using technology similar to that used in applying temporary tattoos. For some device types, the rigid silicon electronics can be eliminated by integrating the active device elements into the serpentine interconnects themselves. For development of integrated devices, functions that have been demonstrated include amplifiers, temperature sensors, strain gauges, solar power sources, induction couplers and wireless transmitters & receivers for device control. Current devices, however, use wires to connect to external control and power sources. The only three elements in contact with the skin are gold, silicon and polyimide, all of which are FDA approved.
K2.2 Michael Melzer of IFW Dresden extended the family of stretchable electronics from silicon and optoelectronics to now include magneto electronics. Stretchable GMR multilayers are fabricated by depositing GMR thin films on a pre-strained PDMS substrate. Data indicates no loss of magnetic performance through this process to 2.5% strain even though resistance starts to rise above 1.6% strain. For greater detection sensitivity, stretchable spin valves were developed using the same process flow as for the GMR multilayers. After some refinement of the process, they were able to achieve 29% strain without losing functionality or sensitivity.
K2.5 A Gaikwad of City College NY described a stretchable battery embedded in cloth with Zn and MnO2 as the active materials. Cracking and delamination due to flexing and stretching was addressed by embedding these materials in a non-conducting nylon mesh in an earlier version. In the new version, a silver coated nylon cloth is used as the substrate for the Zn electrode and separately for the MnO2 electrode. No delamination or electrical degradation was observed at 100% strain in either the x- or the y-direction. The capacity of 4 mAh/cm2 was maintained even with this stretching 100% level.
C2.6 Yusuke Matsuda of Reinhold Dauskardt’s group at Stanford presented a new class of ULK dielectric materials in work done jointly with IBM and RPI. Moisture-assisted cracking is a pervasive problem with current silica-based ULK material options. Polycarbosilane dielectrics (CLPCS) are introduced, their salient feature being a network of Si-CH2-Si bonds. The films have a dielectric constant 2.3-2.5 with no porosity. In comparison with MSSQ and CDO films, CLPCS has a higher fracture strength, lower density and no sensitivity to moisture-assisted cracking. However, there is some crack growth due to viscoelastic relaxation of C-C bonds.
BB2.6 Susan Trolier-McKinstry of Penn State described a low cost, damage-free microcontact printing method for patterning electroceramic films. PDMS stamps for PZT patterning can be used only one time, but the transfer integrity is good for PZT films 110-130nm thick at ~3µm lines/spaces. Dots 3-4µm with 2-3µm spaces can also be printed faithfully. Alternate stamp material research has led to polyurethane (PU) and composite PU/PDMS enables up to 50 passes for multiple use with a simple solvent wash in between. The PU stamp can print large areas >1cm2 and feature sizes from 5µm to 1cm. Electrical and piezoelectric properties of films so deposited overlapped nicely with films of equivalent thickness deposited by conventional methods.
F4.4 Youn-Seon Kang of Samsung R&D provided a glimpse into the coming 20nm node for PRAM. Challenges include contact size, cell to cell distance, reset current and operating voltage. The 20nm diode contact process includes growth of epitaxial Si in the vias, ion implantation, silicidation, tungsten capping and CMP. Use of a confined structure allows a lower reset current with a larger bottom electrode, suggesting that further reduction is possible. Double pattern lithography is used for the minimum feature sizes. Thermal disturbance between neighbor cells is not observed up to 108 cycles. Samsung is optimistic that PRAM will be a robust NVRAM competitor below 20nm.
BB2.8 Isabel Van Driessche of Ghent U (Belgium) used aqueous solutions of YBa2Cu3O7 for inkjet deposition and patterning of superconducting coatings. Fluorine-free aqueous formulations for chemical solution deposition (CSD) were used to eliminate the toxic BaF2 used in traditional approaches. Conventional methods were used to optimize the solution rheology for inkjet image control. Atmospheric control during annealing reduces the detrimental formation of BaCO3 that is problematic in other systems. Features as small as 40µm were successfully demonstrated; smaller features are likely with further ink formulation.