In this three-part series, SEMATECH's authors cover metrology for FinFETs and 3D memory devices, and defect detection capabilities at 22nm. Read Part 2 on 3D memory metrology here. Part 3, sharing new defect detection technologies, can be found here.The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.
February 9, 2012 -- The 22nm node marks the beginning of a major transition from conventional scaling-driven planar semiconductor devices to complex 3D transistor architectures, redefining future needs for lithographic, defect, and films metrology technologies for high-volume chip manufacturing.
FinFETs raise new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. Similarly, future 3D memory devices (Part 2 of this series) will include multiple gate-level structures defined by high aspect ratio (HAR) trenches and holes in multilayer stacks, which are major gaps in current metrology technology. No in-line non-destructive metrologies have achieved the sensitivity and resolution to image or measure CD, depth, profile, or contamination of such HAR features . In addition, defect metrology inspection and review (Part 3) suffer from low sensitivity and inadequate throughput even for current 22nm defects of interest. To address these challenges, a robust metrology strategy should encompass the extendibility of conventional techniques that are approaching their fundamental limits, as well as development of new technologies.
Planar transistors are reaching their critical performance limitations due to undesirable short channel effects imposed by physical scaling. In 3-D FinFET or Trigate devices, the gate surrounds the channel on multiple sides, resulting in higher drive current , better electrostatic control (lower off-state leakage), and lower supply voltage requirements than planar devices. To continue to scale with Moore’s law, devices having 3D architectures will enter manufacturing in 2012 at the 22nm node.
Metrology demands for 3D structures and their more complex integration steps are considerably greater than for 2D devices. The ability to measure fin and gate dimensions accurately with good precision, and to detect subtle process changes for feedback or feed-forward control is essential to assure good device performance and high yield in high volume manufacturing (HVM). For example, variations in FinFET height (more of a concern on bulk Si substrates) can likewise lead to drive current variability. Sharp fin corners can affect threshold voltage , and gate dielectric undercutting can cause shorts between the gate and channel regions or Ion/Ioff variation. Fin line edge and width roughness, sidewall angle (SWA), profile, corner rounding, and gate dielectric undercutting are also critical process control variables. Some of the critical metrology steps entail critical dimension-scanning electron microscope (CD-SEM) measurements (resist and etch fin and gate CD and pitch; spacer width at the bottom; pre- and post-etch Hi-k/metal gate sidewall thickness on the fin; and sidewall line edge roughness). Additionally, scatterometry is required for fin height and gate profile, CD, and pitch (lithography and etch), buried oxide (BOX) recess under fin, gate height over fin after chemical mechanical polishing (CMP), high-k/metal gate (HKMG) thickness and taper on the fin and recess after gate etch, and spacer profile (Fig. 1a).
|Figure 1a) Cross-sectional diagram perpendicular to the fin showing the gate on the fin with spacer.
||b) Diagram of a basic unit cell of a FinFET, demonstrating twelve important process control parameters.|
Conventional metrology methods used in HVM, such as CD-SEM and optical scatterometry, may be challenged by the increased complexity of FinFETs. While CD-SEM demonstrates superior imaging capability, it has no sensitivity to fin height, layer recess, or SWA. Scatterometry is useful for FinFET metrology, but greater parameter correlation increases the measurement uncertainty, similar to increasing the number of variables in an equation. In Figure 1b, showing a diagram depicting a gate-on-fin structure, twelve parameters must be solved by the scatterometry software rather than only the five or six parameters typical for 2-D devices. One possible approach to improve the performance of metrology on complex structures is hybrid metrology, which combines the strengths of two or more metrology toolsets to provide a more comprehensive measurement of the same parameter than the individual techniques. Data obtained from one tool must be shared with another tool and used in a complementary or synergistic way to enhance the resolving power of both tools, thereby improving measurement uncertainty .
Several new metrology techniques are being explored at SEMATECH to improve measurement performance on FinFETs, including new technologies such as critical dimension small angle x-ray spectroscopy (CD-SAXS) . The shorter wavelength (1.54Å for Cu Ka) for CD-SAXS and the lack of material dependence (no n and k sensitivities) allow measurements on smaller devices with less parameter correlation. Pitch and pitch variation can be obtained from major reflections and intensity decay with increasing order. The CD-SAXS envelope functions correlate to geometric form factors, and line width roughness (LWR)/line edge roughness (LER) information can be obtained from peak-broadening. Mueller matrix scatterometry  provides additional structural information associated with up to 16 spectral components compared to conventional scatterometry, which is important in measuring anisotropic 3D structures.
Dopant and carrier metrology for conventional planar devices has been performed primarily using secondary ion mass spectrometry (SIMS) and sheet resistance metrology on test pads. However, FinFET structures require novel ultra-shallow junction implant strategies because of shadowing effects on densely packed fins from conventional tilt implants. Metrology capable of measuring dopant and active carrier concentrations on vertical structures is needed, but currently poses a significant challenge. Three-dimensional atomic probe tomography (3D-APT)  combines field evaporation with time-of-flight mass spectrometry and a position-sensitive detector to provide atomic resolution imaging of the semiconductor device, including dopants. Similarly, scanning spreading resistance metrology (SSRM) is a candidate for active carrier metrology at nanometer spatial resolution. SSRM has demonstrated excellent performance in conjunction with 3D-APT and SIMS . Transmission electron microscopy (TEM) techniques such as energy-dispersive X-ray (EDX) and electron energy-loss spectroscopy (EELS) are valuable in determining dopant concentration and distributions. As these implant metrology techniques are destructive, in some cases, it may be possible to create sacrificial test structures on selected die without affecting subsequent processing. Optically based implant metrology will also be more difficult on sidewalls and on structures having optically opaque layers.
Conclusion, Part 1
As device technology transitions from traditional scaling to new architectures, new application needs are driving metrology towards evolutionary and revolutionary shifts in technologies and methodologies.
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Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.
Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).
Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.
Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.