In this three-part series, SEMATECH's authors cover metrology for FinFETs (Part 1) and 3D memory devices, and defect detection capabilities at 22nm (Part 3). The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.
February 16, 2012 -- The 22nm semiconductor node marks the beginning of a major transition from conventional scaling-driven planar devices to complex 3D transistor architectures, redefining future needs for lithographic, defect, and films metrology solutions for high-volume manufacturing. Future 3D memory devices will include multiple gate-level structures defined by high aspect ratio (HAR) trenches and holes in multilayer stacks, which are major gaps in current metrology technology. No in-line non-destructive metrologies have achieved the sensitivity and resolution to image or measure CD, depth, profile, or contamination of such HAR features . In addition, defect metrology inspection and review suffer from low sensitivity and inadequate throughput even for current 22nm defects of interest. To address these challenges, a robust metrology strategy should encompass the extendibility of conventional techniques that are approaching their fundamental limits, as well as development of new technologies.
Memory producers are migrating beyond planar designs to build multiple levels of gates into 3D structures. These vertical architectures lead to new challenges in semiconductor processing technology . As shown in Figure 2, the basic building blocks of these features are deep, HAR trenches and holes in oxide, silicon, or multiple alternating layers of oxide and silicon.
|Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.|
3D memory structures present many metrology challenges due to their HAR characteristics. HAR contact holes and trenches at ITRS half-pitch dimensions are known gaps in CD and profile metrology; these same measurement limitations have, to some extent, already been apparent with etched contact holes and shallow trench isolation (STI) trenches in logic for recent ITRS nodes. Furthermore, the problem is increasing with shrinking dimensions. HAR etching is difficult, with 30:1, 40:1, or even 60:1 ARs necessary to form a vertical circuit path among stacked gates.
Process control of the bottom of the CD, profile, and detection of polymeric etch residues is required for HVM. While TSVs may have a similar or higher AR, they are comparatively huge -- 3D memory device features will include hole and trench structures with bottom CD sizes at ITRS node dimensions , from 0.5 to 2µm deep. This introduces an entirely new set of gaps in metrology capability as the quest for non-destructive measurements of such features has yet to achieve the necessary sensitivity and resolution. Moreover, the physics of these measurements is incompatible with the extremely deep and geometrically confined volumes involved.
Charged particle imaging techniques such as CD-SEM and helium ion microscopy (HeIM)  have sensitivity limitations arising from sidewall charging, as only a small fraction of scattered particles follow escape trajectories that reaches the detector. Many optical techniques, especially those that operate off-axis near the critical angle, suffer from a very small fraction of the interrogating light reaching the feature bottom, and reflect upwards to the detector. Thus, in most cases, the various metrology techniques in their present forms will suffer low signal-to-noise ratios (SNRs) on such features.
Many technologies are being explored at SEMATECH to enable HVM of HAR features, including new technologies such as critical dimension small angle X-ray spectroscopy (CD-SAXS) , HeIM , and through focus scanning optical microscopy (TSOM)  and variations of existing technologies, such as Mueller matrix  and normal incidence scatterometry (polarized reflectometry), model-based infrared reflectometry (MBIR), high voltage SEM (HV-SEM) , environmental SEM (e-SEM) , and conventional low-voltage CD-SEM. Results are still forthcoming, but CD-SAXS and scatterometry at normal incidence, MBIR, and HV-SEM may have some capability in this application space. CD-SAXS is currently a lab technique, but X-ray sources with higher brightness offer possibilities for transforming this technique into a feasible HVM metrology tool. MBIR takes advantage of the transparency of the various applicable materials to infrared and thus may have sensitivity to some feature aspects. HV-SEM is being demonstrated as useful in providing the capability to charge HAR holes in such a way that reflected incident or secondary electrons can more easily escape the bottom of the feature. Normal incidence scatterometry may be feasible as more incident light can reach the bottom for potentially improved SNR.
Conclusion, Part 2
Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.
Miss Part 1 on FinFET metrology? Read it here.
Move on to Part 3 on new defect detection technologies here.
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Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.
Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).
Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.
Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.