July 1, 2011 - Switching the heating of a wafer during rapid thermal processing (RTP) to the backside of the wafer improves heat distribution and uniformity and widens the temperature range, all of which should be of particular benefit as process technologies shrink to and below the 2Xnm generation, says Applied Materials, with the introduction of its new Vantage Vulcan RTP tool.

Historically with RTP, Si wafers are heated to 400°C-1100°C for a few seconds for anneals and oxidation. But thermal budgets are getting tougher as technologies scale: chipmakers use RTP/anneal at multiple steps in advanced transistors: source/drain, silicide, interlayer dielectric and high-k densification, and now with new FinFET architectures, fin implant. Bigger die increase the within-die uniformity (500mm² for a 40nm graphics chip, vs. 150mm² at 130nm), which means less margin for error with any variations in thermal processing -- i.e. "temperature microclimates," essentially different heat zones (similar to how a dense cityscape traps significantly more than an open field). Temperatures also are a function of process times, too. Changing design rules and "binning" are being employed to combat these effects, noted Sundar Ramamurthy, GM of frontend products in AMAT's SSG division, but there's little room for error -- high-performance apps can get away with some leakage, but others can't. And as chips get larger that means managing across larger scales with more temperature variability and those thermal budgets get even tighter.

AMAT's solution: use uniform heating on the unpatterned backside of the wafer, which it says results in a 3× decrease in nonuniformity -- <3°c>
Some "creative engineering" (which wasn't elaborated upon) enables "extreme" cooldown rates and a broader range of temperatures, close to room temperature (~75°C-1300°C). Closed-loop control -- with sensors specifically designed for low temperatures, developed by AMAT and proprietary -- can dynamically control the wafer temperature. AMAT wouldn't say whether or how it had to rethink the algorithms to collect data to accommodate backside heating.

The tool is currently "in place" at several "top chipmakers" for spike anneal, Ramamurthy said, with demonstration of validation of performance. (Since the tool targets <30nm,>
Prompted by an inquiry during the conference call Q&A, Ramamurthy noted that the Vulcan is the only RTP tool to use exclusively backside heating using a lamp-based architecture, and the only one with "such aggressive spike performance." And as to whether not doing active cooling is a limitation, he noted temperature profiles are starting to approach <1sec residence times, and the biggest reduction is in the cooldown, and part of the Vulcan's architecture allows nearly half the residence time.

Ramamurthy also emphasized that the Vulcan RTP tool is in fact complimentary to laser spike anneal (LSA), for which AMAT also has a tool; "there's a bifurcation in thermal requirements," he explained, and a need for lateral diffusion of species. Both tools will be needed for engineering the transistor. (And the Vulcan and Astra can be put into the same platform, for R&D, he added.)

Another Q&A questioner smartly wondered whether the Vulcan's backside heating (with honeycomb lamp arrangement) would better accommodate the coming larger 450mm wafers, and Ramamurthy seemed to support this without specifically agreeing -- in developing the Vulcan, AMAT had to deal with scaling to handle the wafer backside, e.g. the wafer goes around the lamphead, so delivering uniform heat on a larger area is a general area that AMAT is familiar with. (And the pyrometry of the aforementioned temperature sensors would be independent of wafer scaling anyway.)

And with discussion of <3xnm transistor structures, part of the debate between gate-first/gate-last high-k/metal gate (HKMG) has been that gate last isn't as affected by anneal temperatures. Ramamurthy didn't elaborate whether any customers are qualifying the Vulcan on gate-first at <28nm, when that HKMG inflection point is happening -- though he pointed out that there has been feedback on multiple product types and multiple flows, and some chipmakers are pursuing parallel tracks.