December 30, 2011 -- With 22nm CMOS in production at the end of 2011 and the manufacturing ramp continuing through the end of 2012, volume production faces numerous manufacturing and integration challenges. Application-specific requirements can lead to several integration approaches in order to achieve device performance. As such, there is an expectation that diverse architectures will be implemented in advanced 22/20nm transistor technology.
While the introduction of the first 3D (trigate) transistor based microprocessor will happen at the 22nm node, the majority of semiconductor manufacturers will focus on planar replacement gate technology. Scaled high-k based gate dielectrics are considered absolute for this node, with physical thicknesses of the deposited materials approaching 10Å for the most aggressive high-performance applications. Stringent leakage specifications for low-standby power applications also mandate a transition to replacement gate high-k/metal gate (HKMG) technology. However, gate-first high-k 22nm devices are still being developed for niche high-performance chips, as well as cost-sensitive devices such as DRAM access transistors. Although stability remains a concern with high-k gate dielectrics fabbed with gate-first high-temperature anneals, the first high-k access transistor arrays for mobile DRAM chips are expected to be released at the 22nm node. Regardless of integration scheme, long-term gate-stack reliability under extended voltage stressing is a primary area of optimization.
The majority of current integration challenges lie around the implementation of metal gates for both gate-first and replacement-gate devices. Conventional approaches, such as using a plurality of metal films to tune work functions for nMOS and pMOS, are difficult to maintain because of the ever-shrinking real estate available. Scaling the metal physical thicknesses can alter work functions and diffusion barrier properties significantly, making target threshold voltages quite elusive. These challenges are somewhat mitigated for depleted, three-dimensional transistors since effective work function targets are not as aggressive. However, there is a more stringent requirement for extremely conformal coverage of higher aspect ratio structures. Deposition technologies such as atomic layer deposition (ALD) remain a key pathway to enabling ultra-thin gate stack high-k and metal gate layers for both planar and 3D devices.
Strained silicon technology continues to drive performance gains at 22nm. Epitaxial SiGe films in the source/drain regions have been used for pMOS strain for a few generations, but at the 22nm node, nMOS strain technology will likely be introduced. There are two approaches under consideration for nMOS strain: epitaxial Si:P and epitaxial Si:C:P. While epitaxial Si:C:P in the source/drain regions of the transistor have been demonstrated by a number of groups as a uniaxial stressor, the integration challenges (film stability, sheet resistivity) associated with incorporating high levels of C (>1.5%) make this solution less attractive than Si:P. Si:P epi is more easily integrated into the nMOS device than Si:C:P, but doing so comes at a cost of lower device performance enhancement because of lower strain levels. However, Si:P epi still provides benefits of drive current enhancement via low resistivity and accurate placement of the source/drain junction, since it is performed by etch and epi processes rather than implant and diffusion.
In the past, advanced technologies such as strained silicon and HKMG transistors have been limited to high-performance desktop and server applications. However, the global demand for high-performance handheld devices will drive widespread adoption of this technology for low-power applications at the 22nm node.
Mohith Verghese is technical product manager of the Thermal Products Business Unit, ASM America.
This article is part 6 of a series of 22nm forecasts from Solid State Technology contributors.