December 28, 2011 -- According to the Mayan Calendar, the world is supposed to end in December of 2012. The microprocessor will be over 40 years old, and 22nm devices will be ramping in production. 2012 promises much for the semiconductor industry, and the world.

The chip industry will see two different device types ramping in 2012: second-generation 2xnm NAND flash, and Intel’s 22nm microprocessors. Each of these technologies presents different challenges to manufacture and yield.

In 2012, Gartner expects 22nn technology to account for 24.8 million square inches (MSI) per quarter of the total industry capacity. This accounts for less than 1% of the total capacity.

NAND flash, with the critical dimensions and layout, will continue to drive lithography using double-patterning, and perhaps triple-patterning. Atomic layer deposition (ALD) tools will be challenged to deposit films as thin as 4nm to achieve the proper gate dimensions and device electrical characteristics. The number of electrons on the gate continues to shrink, making reliability and repeatability of deposition and etch processes critical to NAND yields. 2xnm and 1xnm NAND are expected to be roughly 4% of the 19,000 Petabytes total production in 2012

22nm logic will begin to ramp in late 2011 with production-level volumes being reached in 2012 as Intel rolls out the 22nm Ivy Bridge products. The trigate transistor brings the third dimension to transistor technology. The trigate transistor is combined with Intel’s well-established high-k metal gate (HKMG) technology. The trigate transistor presents different etch and deposition challenges to fab equipment than NAND flash. The sidewalls need to be very close to 90° with minimal edge roughness, relying on the silicon etch process. Sidewall doping needs to be very conformal, which can be accomplished in part with the epitaxial process, but the doping process will be critical to transistor uniformity across the device and the wafer. ALD uniformity will be necessary for success of the transistor performance. Lithography, while challenging, appears to be a single-pass using immersion technology -- not quite as complex as the NAND lithography.

Read Freeman's commentary in Intel hits 22nm stride with trigates

For the semiconductor fab equipment manufacturer in 2012, it is business as usual. Develop and deliver equipment that meets or exceeds the critical process specifications of device designers. For the device manufacturer, it will be about ramping up a learning curve to improve yield, while developing the next generation of technology.

And let’s just hope the world doesn’t end before we get to 14nm.

Dean Freeman is research VP at Gartner Inc.

This article is part 1 of a series of 22nm forecasts from Solid State Technology contributors.

Read part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: At 22nm, the focus is first order effects by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group