December 12, 2011 -- Dennis Buss, a visiting scientist at the Massachusetts Institute of Technology (MIT) and consultant at Texas Instruments (TI), presented "Research in self-powered electronic systems (#10.4)" at IEEE's International Electron Devices Meeting (IEDM) recently. He shares key results here.
Ultra-low-power systems operate in the range of a 100microWatt to a few milliVolts; one way to do this is to go to ultra-low voltage -- around 0.5volt is typical. Medical monitoring/health monitoring electronics can become self-powered systems that would preclude the use of wires or batteries that need to be removed and replaced. Also, wireless sensor networks (WSN) can be used for such applications as smart buildings that do not require a permanent source of energy.
One key result in Buss' IEDM paper was an MSP430 chip designed to operate below threshold: a VDD of around 0.3V. Compared to the commercial product, the chip achieved an energy/operation reduction of a factor of >10x. The chip had on-chip SRAM, on-chip DC/DC converter and a fair amount of logic.
Another result: an ultra-low-power medical DSP fabricated in a 130nm low-leakage process. This chip operated down to 05.V and surprisingly used accelerators. (e.g. FIR and FFT filters, and other algorithms commonly used in medical monitoring).
Two technical challenges exist. Random dopant fluctuation-induced local variations occur. When you operate at very low voltage, the variations in threshold have a huge -- exponential -- effect on logic timing. "There is no way to make a corner model that comprehends accurately the effect of local variations," says Buss. What his team shows is that, at low voltage, the 3-sigma stochastic delay resulting from local variations can exceed the corner delay, so it must be accurately understood. When we design chips today, Buss says, the predominant process variation is global -- affecting all logic gates on the chip in the same way. For example, if the gate length is a little on the long side, it's probably long for all the devices on a chip. "If we're interested in the slow corner, we can generate a set of models that will comprehend the 3-sigma worst-case global delay for these variations. We don't simulate the nominal models, we simulate to the worst-case slow and worst-case fast models. In the case of random dopant fluctuations, the transistors are not all affected in the same way; in fact, they are all different. When you combine the stochastic effects of different transistors, you have to add them in quadrature (like the square root of the sum of the squares) and this requires a new methodology for timing."
Another technical challenge is systems aspect. In some sense, we've demonstrated all the pieces -- logic, AFE, A/D converter, ultra-low-power radios, energy management, switch capacitor DC/DC converters, and energy harvesting devices -- but we still don't have a system that responds to real needs, Buss says. Two system aspects are particularly demanding: the needs of computation vary dramatically (throughput) and unreliable energy sources that require battery back-up.
Listen to Buss discuss the paper:
See more paper summaries from IEEE's IEDM:
- imec presents MEMS energy harvester at IEDM
- SuVolta's DDC transistor technology @ IEDM
- SEMATECH’s SILC ~10% and HKMG lifetime; ALD BeO a viable gate stack IPL solution
- Cornell, SRC develop RF MEMS technologies
- IBM displays via-middle TSV process for die stacking
- Intel clarifies 32nm NMOS stress mechanism at IEDM 2011