December 30, 2011 -- At the 20nm semiconductor process node and beyond, multiple masks -- each with complex mask shapes -- are needed to achieve sufficient process window in the wafer for the critical layers. The complex shapes are created by optical proximity correction (OPC) adding a large number of sub-resolution assist features (SRAFs) and main features requiring complex contours.

At these advanced nodes, where these assist features are smaller than 80nm in width, the challenge lies in printing the image faithfully on the mask. Because of the radius of the combined short-range blur from the electron beam (e-beam) used to write masks plus mask-process effects, a 60nm square feature, for example, does not print as a square, but as a smaller-sized circle with poor dose margin (DM).

Wafer simulation can provide insight into what will print on the wafer. However, all traditional wafer simulation technologies assume that mask writing is accurate within a small corner-rounding effect. Accurate mask-wafer double simulation is a new, required step for the 20nm node and beyond because corner rounding becomes the dominant effect with these small features, particularly when they have complex shapes that are not just orthogonal rectangles.

Mask-wafer double simulation is also necessary for advanced nodes because of the explosion of mask data volume caused by all the complex images required for advanced designs. Cost-effective manufacturing of semiconductors requires both reasonable mask write-times and good wafer yield. But more complex masks that produce good wafer results often cost too much in terms of mask write-times to be practical. Trade-offs must be made between results on the wafer and mask write-times; therefore, engineers require information on how a particular mask image will print, both on the mask and on the wafer, coupled with information on the shot-count required to produce that image.

Accurate mask-wafer double simulation for intelligent trade-offs should include views into each step of the mask/lithography process, including e-beam simulation, DM/edge-slope analysis, mask-process simulation for develop, bake and etch effects, lithography simulation and lithography contour simulation. The simulations must run fast enough to be interactive, so that various trade-offs can be compared in a reasonable timeframe.

As the semiconductor industry moves toward each new process node, new challenges arise. At the 20nm process node, mask fidelity and shot-count explosion are two of those problems that are now constraining the wafer results. The industry will need to transition from the traditional bundled models that assume mask fidelity to the separated-model approach provided by mask-wafer double simulation.

Aki Fujimura is CEO of D2S Inc. The company is managing sponsor of the eBeam Initiative.

This article is part 4 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group