imec advances CMOS beyond silicon to Ge, III-V

December 14, 2011 -- Marc Heyns, fellow at research consortium imec, discusses the group's work on chip fab materials beyond silicon, namely, germanium (Ge) and III-V, presented in paper 13.1, "Advancing CMOS beyond the silicon roadmap with germanium and III-V devices," at IEEE's International Electron Devices Meeting (IEDM) this month.

imec has been working for several years on CMOS devices with high-mobility channel substrates. Initially imec used germanium for pMOS devices and III-V for nMOS devices. This had led to a whole new series of technologies, advancing "what you can do with CMOS beyond what you can do with silicon," Heyns says.

To implement these materials, the first step is to get them onto a 300mm or -- in the future -- 450mm silicon wafer for production. imec does this with aspect-ratio trapping, where Ge and III-V are regrown in trenches etched in the silicon. This yields a high-quality material, but is not without challenges. imec developed a double-step technique -- etching a hole into the silicon, depositing Ge in it, and reflowing the Ge -- to take care of anti-phase boundaries.

Another problem is materials passivation. imec tried ultra-thin Si layers, atomic layer deposition (ALD), and sulfur passivation, which Heyns says has yielded very good results (details in the podcast below). With ALD, Heyns says the precursor type is very important.

Also read: imec claims RRAM is smallest based on HfO2

imec also has been studying defects in the high-k layer. Sulfur passivation has been shown to lower the defect count in the high-k layer.

Then imec moved to making devices with these materials, and has been working on that for the last few years with good results, especially in SiGe. What's next? Introducing strain. imec showed results at IEDM on how it introduced a Ge Fin to make a strain in germanium, as well as other methods.

Finally, Heyns says, once the FinFET is developed, you must look to making other novel devices, using nanowires and other advanced materials like gallium and arsenide. Heyns covers the use and benefits of these novel materials in the latter half of the podcast below.

When will Ge and III-V be seen commonly in chips? FinFETs are being introduced today, and as the industry goes to more advanced production nodes, these materials will be useful options. But, Heyns points out, this is all speculation for the moment.

Listen to Heyns' full interview about the paper with contributor Debra Vogler below:

 

Subscribe to Solid State Technology

More from IEDM:

Self-powered electronics: Achievements and challenges

imec presents MEMS energy harvester at IEDM

SuVolta's DDC transistor technology @ IEDM

SEMATECH’s SILC ~10% and HKMG lifetime; ALD BeO a viable gate stack IPL solution

Cornell, SRC develop RF MEMS technologies

IBM displays via-middle TSV process for die stacking

Intel clarifies 32nm NMOS stress mechanism at IEDM 2011

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.


VIDEOS

Electroiq 2 EIQ2

NEW PRODUCTS

EV Group rolls out EVG120 processing system

May 7, 2013 EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, t...

Quartz Imaging introduces automated measurement for semiconductor images

April 30, 2013

It can be very time-consuming for engineers to measure the various features of an X-SEM image of a semiconductor device.

Axcelis launches Purion XE high energy implanter

April 30, 2013 Axcelis Technologies, Inc. today announced the introduction of the Purion XE next generation single wafer high energy implanter...

EMS debuts low-cost conductive LED die attach adhesive

April 29, 2013 Engineered Material Systems debuted its CA-105 Low-Cost Conductive LED Die Attach Adhesive for attaching LEDs and other small s...

TECHNOLOGY PAPERS

Rapid Defect Indentification with Layout-Aware Diagnosis

Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are...

Flip Chip Devices get Flat and Happy

Thin is definitely in, but what our modern flip chip devices really want is to be flat and happy! As flip chip die have become increasingly thinner in recent...

WEBCASTS

Surface Cleaning and Preparation

This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL...

450mm Status Report

Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business...

Join The ConFab discussion

Tue Feb 26 11:27:00 CST 2013

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

05/01/2013
Volume 56, Issue 3

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS