December 29, 2011 -- With the 22nm node now ramping toward volume production, it is an opportune time to assess 22nm’s technological components and impact on semiconductor process development, manufacturing and TCAD simulation.

In lithography, despite advances made in extreme ultraviolet (EUV), 193nm immersion is still the workhorse, but has double-patterning as a new component for defining the critical layers.

It is in transistor architecture where the 22nm node marks a significant milestone, with Intel’s introduction of trigate devices, the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. While other 22nm node technologies will continue using planar silicon MOSFETs, the introduction of trigate devices at 22nm is likely to foster their wider adoption at 14nm and smaller nodes, although fully-depleted SOI (FDSOI) technology is still a contender.

To harness the full potential of these 3D devices, new wafer processing technologies are being developed to controllably dope the fin sidewalls and to stress the fins to boost device performance. To support these efforts, 3D process and device simulation (TCAD) is now required as a way to guide and optimize the chip fabrication process. An important example of the need for 3D TCAD simulation is in the process optimization of SRAM cells, where stress and doping proximity effects require that all transistors comprising the SRAM be simulated in a single structure. This type of TCAD simulation has only become possible in the past year, with advances in 3D structure generation, mesh generation, and parallel algorithms.

Regardless of transistor architecture, the impact of process variability on device and circuit performance has emerged as a significant concern at 22nm. Effects that until recently were negligible or could be mitigated with improved manufacturing control are now first-order effects. The number of dopant atoms in the channel of a 22nm transistor is now small enough to reveal fluctuations in the current simply due to their random placement. This effect, known as random dopant fluctuation (RDF) is a primary source of variation. RDF, line edge roughness (LER), variation in the workfunction of metal gates due to their constituent grains, layout-induced stress variation and other sources of process variation ultimately manifest themselves as variations in device performance, particularly in the threshold voltage and on current. Recent advances in TCAD models and numerics allow efficient simulation of device variability, enabling the systematic analysis of how each source of variation affects device performance.

In the interconnect layers, the 22nm node is largely a scaled version of the 32nm node, but here too, several issues are exacerbated. Mechanical stress in the copper/low-k interconnect stack, a well-known precursor in several reliability failure mechanisms, must now be analyzed in more detail, including the complex 3-D geometries and the full stress evolution of the process, so that reliability engineers can detect hot spots during process development, not in production when corrective action is very costly. Beyond mechanical stress, electromigration, stress migration, and other interconnect reliability mechanisms are also being addressed with TCAD.

The picture that emerges from this assessment is one of rising complexity, more physical phenomena at play and costlier equipment and wafer processing. These challenges will only become more severe at 14nm and beyond, providing a strong motivation for the development of increasingly sophisticated process and device simulation tools to offset them.

Howard Ko is senior vice president and general manager of the Silicon Engineering Group at Synopsys Inc.

This article is part 3 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group