December 28, 2011 -- The transition from 32nm to 22nm silicon will have a major impact on the semiconductor design community. The most obvious is the increase in process variation. This affects timing, but more importantly, it affects power. Because of this, we are seeing a dramatic increase in the 22nm process design rules. More and more design teams will decide to leave the IC layout portion of the design to the experts.

The effects of 22nm on the EDA vendors will be a combination of opportunity and shrinking IC layout seat count. Although the new design rules moving toward structured silicon reduce the need for optical proximity correction (OPC) tools, the move to double-patterning lithography raises new challenges for OPC tools, resulting in overall market growth. The variation problems will also drive the demand for design-for-yield (DFY) tools. The new variation challenges require that IC place-and-route tools actively ensure the robustness of the final layout, therefore, growing the IC layout market for those tools that keep up with the 22nm challenge.

This shift in responsibility won’t give the circuit designers a free ride. They have more than enough to do to keep the power problem under control. For all the work we’ve done in decreasing power at the IC CAD level, we need to address the 80% of the power problem that is introduced during the design process.

Design for 22nm puts over two billion gates at design engineers’ disposal. There are a lot of reasons why they aren’t using that many: cost is one, design time is another, but the main one is power. One of the ways a designer can get around the power problem is to simply turn off unused portions of the circuit, but this “dark silicon” is growing as these designs get larger. The technique is especially useful in applications-driven designs such as cell phones. You can only do so many things at a time on a cell phone, yet users are demanding more and more functions be made available in the next-generation smart phones.

The one tradeoff microprocessor vendors don’t like to talk about is frequency. An engineer has three things to play with: varying the size of the design, the power (or energy) used by the design, and the frequency. In the mobile community the problem isn’t power, the power envelope is a requirement. That leaves the gate count and the frequency as the two variables. The average high-end mobile design only uses about 20% of the available silicon. In an app-driven world, the pressure will be to use more gates. If something has to move it must be frequency, and it has to move down. Even today’s cell phone designers laugh at the microprocessor vendors that brag about their multi-GHz processors. What they really want is a processor architecture that will allow them to operate multiple applications at 300MHz.

So welcome to the world of 22nm design. It should be fun.

Gary Smith is the founder and chief analyst of Gary Smith EDA.

This article is part 2 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group