STM completes 20nm chip tapeout with MENT design tools

11/07/2011

November 7, 2011 - BUSINESS WIRE -- Mentor Graphics Corporation (NASDAQ:MENT) completed a 20nm test chip tapeout with STMicroelectronics (NYSE:STM).

Mentor is pursuing a design-to-silicon framework for next-generation semiconductor nodes with the Olympus-SoC, Calibre and Tessent silicon test and yield analysis products. "The 20nm node has...new requirements including double patterning [lithography]," noted Pravin Madhani, general manager of the Mentor Place and Route Group. Process complexity, variability, large design sizes, low power requirements, and more are also considerations, added Philippe Magarshack, group VP at STMicroelectronics Technology Research and Development. The test chip was implemented using the Olympus-SoC place-and-route system, and verified using the Calibre nmDRC verification and double patterning platform (which is used by R&D teams at STMicroelectronics).

STM is a teaching customer and strategic investment partner in the DeCADE program for 20nm enablement. The joint-development project named DeCADE builds on advanced design technologies for system-on-chip (SoC) development. DeCADE reinforces the Crolles cooperative R&D cluster, which gathers partners that develop and enable low-power SoCs and value-added application-specific technologies, and is a project developed within the framework of the Nano2012 program. Nano2012 is a strategic R&D program, led by STMicroelectronics, which gathers research institutes and industrial partners and is supported by French national, regional and local authorities.

The Olympus-SoC place and route system is a complete netlist-to-GDSII system and is built on patented concurrent multi-corner multi-mode (MCMM) optimization, high capacity data model, advanced low power capabilities and integration with the Calibre platform for faster manufacturing closure. The OpenRouter architecture of the Olympus-SoC product enables native invocation of Calibre engines during design and uses the foundry signoff decks to ensure that the resulting layout is decomposable for multi-patterning, in addition to being DRC/LVS/DFM signoff clean.

Mentor Graphics Corporation (NASDAQ:MENT) makes electronic hardware and software design products and services. World Wide Web site: http://www.mentor.com/.

Subscribe to Solid State Technology

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. 


VIDEOS

Electroiq 2 EIQ2

TECHNOLOGY PAPERS

Automated Test Creation for Mixed Signal IP using IJTAG

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis

This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...

WEBCASTS

Innovation in Semiconductor Manufacturing Instrumentation

As the industry is incorporating more MEMS devices with integrated magnetic sensors, they are encountering challenges that cannot be overcome with ...

3D and 2.5D Integration: A Status Report Live Event

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

Oh, snap!: Pics from The ConFab

Sun Jun 03 19:09:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

Volume 56, Issue 1

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS