November 16, 2011 -- ICs developed at advanced technology nodes of 65nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues, as devices and structures get smaller and smaller. These factors make yield management a big challenge for wafer fabs. Data failure analysis (DFA), electrical failure analysis (EFA), and physical failure analysis (PFA) are three important methods for yield management. DFA is to analyze field failure data such as correctness and performance. EFA and PFA are to identify the physical location of the failure, find this physical failure in the chip, and then link it to a process step to fix in-line problems. However, traditional wafer-level EFA and PFA methods on advanced technology products are no longer sufficient. It is important to trace the implementation of the solution to ensure that no side effects from these actions have created new failures, and to make sure that the failure will not appear again.

Overview of yield management in fabrication

Yield management in the foundry involves many players. Technical development, process integration engineers, inline process engineers, and reliability engineers all have responsibility for meeting the expected yield. Technical development engineers in charge of process development and optimization give technical and design support for inline production wafer manufacturing. Process integration engineers monitor inline defect sources for defect reduction and control the quality of wafer acceptance test (WAT) results. Inline process engineers assure the machines are working smoothly and improve the process margin. Reliability engineers monitor inline production wafers reliability performance. But inline process always has variations, which will induce wafer low yield or reliability/quality issues. When the customer or test feedback finds a yield issue, the product engineer is in charge of yield analysis and will apply DFA, EFA and PFA. The traditional physical and electrical failure analysis is (EFA and PFA) shown in Fig. 1.

Figure 1. Traditional EFA and PFA methods.

When logic or memory products fail, DC test data analysis is the first step. From this we can determine whether bad dice have different DC currents and waveforms from good ones, which helps with fault localization. When the outliers are found, techniques to identify “hotspots” such as emission microscopy (EMMI), liquid crystal (classical hotspot method), and optical beam induce resistance change (OBIRCH) are employed. These techniques are the foundry’s basic practices, and traditional ways to localize the failures. After fault localization, PFA is the next step. Delayering, optical microscopy (OM), cross-sectioning, scanning electron microscopy (SEM), transmission electron microscopy (TEM) analysis, and other chemical process are used. The last stage is to identify the physical root cause for the failure, then feed that root cause back to the fab so that the problem can be corrected.

The traditional flow is based on the important fact that bad samples have different DC currents than good samples. If there is no difference in current between bad and good samples, the fault locations can be difficult. Memory products can use bitmapping to localize the fault address, and then PFA can be applied. However, other failure modes for logic products (Scan/ATPG/Function/BIST/Analog) are almost impossible to catch using traditional PFA methodology.

Figure 2. Failure distribution.

Figure 2 shows yield loss distribution in 25 key logic and mixed-signal products at current technology nodes in mass production phase. Logic failure weight is 49.3% of the total failures. What can be done about that half? Engineers need a way to locate the SCAN/ATPG/Function fail defect, which has led to the introduction of logic mapping scan diagnosis.

Scan diagnosis

Design-for-test (DFT) is now a regular part of the IC design flow for logic test. Original functional testing exercises a chip’s intended functionality using simulation vectors or vectors generated by hand. In general, these tests tend to be very expensive to generate, expensive to run, and the quality is not guaranteed. In addition, functional vectors do not facilitate diagnostics of failing devices. To simplify logic testing, enable automated test pattern generation, and facilitate diagnosis of failing devices, scan chains are embedded into the logic circuit. Figure 3 shows a scan chain inserted in a small circuit.

Figure 3. Scan insertion.

Scan diagnosis is enabled by DFT. It is based on scan test fail information from the test equipment (ATE), test patterns, and design description. This data is then put through complex calculations by EDA tools that show the fail locations in the logical scan circuit. A diagnosis solution typically reports a failure by net name, cell name, or cell pin name along with the suspected failure type identification and scoring. The layout representation of the design (such as LEF/DEF) can be used to find the failure physical location in the real layout and also increase diagnosis resolution from logical candidate to specific layout segment. On the other hand, accurate and physical oriented diagnosis result can also pave the way to yield analysis but the real challenge is how to analyze volume data. Using PFA to find the real failure in the chip is the next step. It is very useful for the foundry to rapidly and accurately identify and isolate scan yield-limiting defects.

Figure 4. Example of scan diagnosis for scan failure.

Figure 4 shows an example with seven layers of copper interconnect on 90nm technology node. The PFA for the device confirmed that particles on the surface of the dielectric were the root cause of the CT (ConTact) missing. Fixing this problem improved baseline yield about 8%. It is impossible to catch this kind of scan failure with the traditional hotspot identification method.

Using scan diagnosis to drive yield

Yield challenges for semiconductor companies vary based on many factors. As manufacturing ramps up for a product, yield limiting signature is often observable, and it is always caused by more than one factor. The challenge is to identify the root cause rapidly. In the ramp up phase, wafer maps always show an obvious pattern, and it is easy to select samples to do failure analysis because every sample can identify the failure root cause. Once the worst issues are resolved, the product may be reaching the mature yield phase. In this phase, a yield limiting factor is always a singularity and caused by systematic issues, and wafer failure maps usually show random patterns. This hidden systematic failure may be subtle, but will cause less optimum yield. The challenge in this mature yield phase is in selecting failure analysis samples to find the systematic issue in the random failing pattern. Figure 5 shows typical wafer maps of ramping yield and mature yield.

Figure 5. Wafer maps of ramping yield and mature yield.

In the above two yield analysis scenarios, the first one can be solved by scan diagnosis alone. Scan diagnosis provides accurate and timely data to the foundry, and has proved to be valuable when attempting to increase products yields.

In the second scenario, scan diagnosis along with traditional failure analysis techniques may not be sufficient. When the foundry sees random fail patterns on one wafer, random samples will be selected to do scan diagnosis and PFA. All PFA results that include samples with many different failure modes will be collected, then summarized and compared with all results. The problem that leads to most of the failures is considered the root cause of the random pattern failures. For example, for one wafer that showed a random low yield pattern, scan fail was the major failure type. Of a total of 50 scan fail dice on the wafer, we randomly selected 10 dice for scan diagnosis and PFA. Two samples showed CT open, two showed metal bridge, two showed tungsten residue, and the other four showed poly bridge. We concluded that poly-bridge is the root cause of the random low yield pattern, poly loop has a systematic issue, and the other six failure results are inline baseline defect induced. In other words, the failure analysis of the six baseline defect samples was a waste of resources and time in terms of root cause clarification. The traditional method to handle random low yield is at the risk of missing true failure. To continue the above example, if the other 40 samples, which were not randomly selected for failure analysis, were checked and all failed with CT open, the conclusion reached by analyzing the 10 samples we selected would be wrong. Can scan diagnosis help to solve this problem?

Statistical analysis of volume diagnosis results can give surprisingly useful results. Every diagnosis process will generate one diagnosis report with lots of information. It includes cell type, cell name, cell coordinate, defect mechanism, circuit logic, physical locations, testing data and so on. With this information, the diagnosis-driven yield analysis solution will classify the results of the scan diagnosis into different categories. This classification step enables the engineer to separate the dice into correlating groups, such as defects in different instantiations of a particular standard cell or defects involving a particular type of via.

Figure 6. Statistical analysis by volume diagnosis.

For example, Fig. 6 shows statistical analysis of volume diagnosis results of an excursion wafer that has 200 scan failing devices, 150 with suspected bridge defects. Of these 150 die, 100 have bridges in the metal2 layer. Of those 100 die, there are 20 with just a single diagnosis suspect, and out of this subset, 10 have high-score results. By leveraging diagnosis data in this way, you can find the suspected systematic defect mechanism (bridge in metal2) before failure analysis, and easily select a device that clearly exhibits this behavior. Then, you can skip the costly physical-localization step and go straight to construction analysis.

Figure 7. Zonal analysis by volume diagnosis.

Another failure filter technique based on volume diagnosis results is called “zonal analysis.” While the distribution of all failing dice may appear to be random, the distribution of dice with one particular diagnosis signature by different zone may be systematic in nature (e.g., Fig. 7). A stacked wafer map or a single wafer low yield map is used to represent all failing dice. The distribution of all failures across the wafer is relatively even. The diagnosis results show all the characteristics of all the failures, such as failing chain, failing cell, failing pattern, etc., and the diagnosis signatures as defect type, failing net, failing layer, failing via, etc. For a given instance, one can only see how many bridge defects occur in the different metal layers. However, just because most of the bridge defects were in one specific layer, it does not directly mean that there is a systematic problem related to that layer.

The engineer could look at the same signature for different zones of the map. If the distribution is relatively similar in all the three zones, it shows random defect distribution, and the engineer can check another zonal type and do analysis again. You can select different classifications such as center, ring and edge to do zonal analysis. Suppose the distribution of bridge defects in one particular layer varies significantly between zones. A wafer map only representing bridges in metal2 might show that these are primarily near the edge of the wafer. This is something that indicates a systematic problem. Using a tool from Mentor Graphics, we automatically performed statistical independence tests for eight different zonal types to find systematic defects in a dashboard. With zonal analysis, the tool can automatically examine the various diagnosis signatures of many failing die and flags those that have an unexpected distribution across the data set.

Product qualification vehicle methodology for advanced processes

In the traditional logic semiconductor manufacturing industry, a test qualification vehicle (TQV) is usually an inline process monitor product with basic SRAM structure. These products are not from a customer; they are designed and taped out by the foundry. SRAM products use the same process as logic products, and it has advantages from a yield ramp point of view. An SRAM design is very simple, with repeated structures. Failures are easy to localize by testing and bit mapping, and foundries usually have rich experience with SRAM DFA, EFA, and PFA methods. Through these TQVs, the fab finds its process weak point rapidly, fixes the yield limiter, and ramps up product yield in a short time. But as semiconductors go deeper into nanometer scaling, more and more failures are not reflected through SRAM. Inline memory-like defect cases take a few percentages of total failures. Some failures related to pattern, timing, and environment are not covered. How can we continue to monitor our process when logic products fail at scan, logic BIST, analog or other functions?

Figure 8. PQV Test Chip.

Because scan diagnosis is capable of identifying most failure mechanisms, foundries need one product to leverage scan diagnosis for inline process monitoring. Different from the TQV or SRAM type test chip, the product qualification vehicle (PQV) is a test chip with multiple heterogeneous modules that is similar to customer designs, as shown in Fig. 8. With this PQV, the foundry and its customer can localize failures and analyze diagnosis results, which shorten the time needed for foundry and customers debug. To move forward for best practice, both customers and foundries still need more collaboration for yield ramp.

Conclusion

A yield management system must continue to monitor inline process performance from multiple sources and provide a high-level view, quickly informing engineers when the inline process shifts. Failure analysis and root cause certification directly influence the speed of inline process correcting. Scan diagnosis provides accurate and timely solutions on scan/function/logic BIST failure analysis, and is an important supplement to traditional failure analysis methods. Diagnosis-driven yield analysis involves deeply diving into both the design and test failure data of the specific device, rather than only relying on manufacturing process data. Consequently, cooperating with the customer can often provide more specific information to guide the physical failure analysis step, and can help uncover design-related systematic issues that are difficult to discover using process data alone. Scan diagnosis data collected in volume can also be exploited for yield monitoring purposes, as a shift in the process performances may lead to a variation in the electrical signature. Thus, scan diagnosis should be added to the other traditional instruments used for yield ramp.

References

1. “The Changing Role of Diagnosis in Yield Analysis,” Test & Measurement World, Dec 2009/Jan.2010 www.tmworld.com.

2. K. Gallie, W. Yang, N.Tamarapalli, “Scan-Based Diagnostics Assists Yield,” Evaluation Engineering, October 2005.

3. “YieldAssist and Its Successful Industrial Applications,” Design-for-Test Whitepaper, December, 2007.

Acknowledgments

The authors wish to thank Zippo Lui of SMIC and Actel Nui of Mentor Graphics for their valuable contributions.

Heng Wei holds a Bachelor’s degree in optoelectronic communication from Tianjin U. and is a senior logic engineer at SMIC, 18 Zhangjiang Road, Pudong New Area Shanghai, P.R.C, ph.: 0086-021-3861000#15365; Heng_Wei@smics.com.

Ting-Pu Tai holds a Master’ degree in electrical engineering from the U. of Southern California and is the DFT marketing manager at Mentor Graphics, Taipei, Taiwan; ting-pu_tai@mentor.com.

Also read: Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM

Subscribe to Solid State Technology