IEDM 2011: Three 5nm FETs battle in ultimate device scaling

 


Current efforts to maintain Moore's Law via scaling are expected to take the industry down into the teens of gate lengths, but there's a lot of debate what happens next with new architectures and exotic materials/processes. Purdue researchers look at three different device designs to survey the playing field at 10nm: carbon nanotubes, graphene nanoribbons, and III-V and silicon ultra-thin-body devices and nanowires. Among their findings: many of them can get good subthreshold swing down to 8nm; nonplanar devices can get good performance even down to 5nm gate lengths; and with identical bandgaps, CNT FETs and small-diameter silicon and III-V nanowires exhibit roughly the same performance, though profile and interband tunneling are critically important. [Paper #11.2, "Ultimate Device Scaling: Intrinsic Performance Comparisons of Carbon-Based, InGaAs and Si Field-Effect Transistors for 5-nm Gate Length"]

Next slide: Straining the limits of CMOS with Ge, III/V

Previous slide: Hollow copper 3D TSVs

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.


VIDEOS

Electroiq 2 EIQ2

NEW PRODUCTS

Spectra-Physics introduces industrial picosecond laser

May 10, 2013 Spectra-Physics, a Newport Corporation brand, introduces Spirit ps 1040-10, an industrial-grade picosecond laser for precision ...

Multitest announces ecoAmp for high-power applications

May 8, 2013 Multitest announces that its ecoAmp high power Kelvin contactor successfully passed a challenging evaluation for an automotive ...

EV Group rolls out EVG120 processing system

May 7, 2013 EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, t...

Quartz Imaging introduces automated measurement for semiconductor images

April 30, 2013

It can be very time-consuming for engineers to measure the various features of an X-SEM image of a semiconductor device.


TECHNOLOGY PAPERS

Rapid Defect Indentification with Layout-Aware Diagnosis

Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are...

Flip Chip Devices get Flat and Happy

Thin is definitely in, but what our modern flip chip devices really want is to be flat and happy! As flip chip die have become increasingly thinner in recent...

WEBCASTS

Surface Cleaning and Preparation

This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL...

450mm Status Report

Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business...

Join The ConFab discussion

Tue Feb 26 11:27:00 CST 2013

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

05/01/2013
Volume 56, Issue 3

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS