To get a better look at what's going on inside a FinFET structure, IMEC researchers eschewed the time-consuming process of combining 2D slices, and instead mapped the 3D carrier profiles of FinFETs (2-3nm resolution) using "scanning spreading resistance microscopy" -- a progressively shifted gate across multiple identical fins. From that they formed a 3D profile, which allowed them to map electrical resistances and infer charge distribution. It's a useful technique, they say, to determine how gate underlap, conformality, raised source/drain doping and other issues affect device performance. [Paper #6.1: "3D-Carrier Profiling in FinFETs Using Scanning Spreading Resistance Microscopy"
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