3D ICs with Cu through-silicon vias (TSV) are getting a lot of attention, but some issues relating to potential damage still have to be worked out -- e.g., having Cu and Si in such close proximity can lead to physical stresses, and their fabrication processes can cause damage too. IBM researchers devised annular (hollow cylindrical) Cu TSVs to connect upper-level wires in a functional 32nm SOI 3D embedded memory module (128-Mb DRAM on top of a 96Mb DRAM, each using 0.039μm2 HKMG). They found no loss of physical integrity or performance degradation, based on extensive thermal cycling (>500 cycles) and stressing (>275°C for 1500 hours). [Paper #7.1: "3D Copper TSV Integration, Testing and Reliability"]
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