| IEDM 2011 slideshow |
| Graphene devices in a 200mm fab |
| Hynix pushes NAND limits |
| FinFETs for sub-20nm SoCs |
| Mapping FinFET carrier profiles in 3D |
| Hollow copper 3D TSVs |
Researchers from IBM demonstrate 200mm wafer-scale graphene devices -- graphene FETs and RF passives -- processed entirely in a standard silicon fab, billed as "a significant step toward moving graphene from an interesting curiosity into a manufacturable technology." Key to this work was building a gate dielectric on the inherently inert surface; to solve this, Si wafers were built with predefined embedded gate structures, upon which were transferred CVD-fabricated graphene layers.
The end result, a proof-of-concept frequency doubler, demonstrated ~25dB conversion gain at 2GHz, which was seen constant from 25-200°C -- indicating the n- and p-transconductance are temperature-independent within that range, which they say is a new finding for CVD graphene-based devices.
[Paper #2.2: "Graphene Technology with Inverted-T Gate and RF Passives on 200mm Platform," S. Han et al, IBM
S.-J. Han, A. Valdes-Garcia, A.A. Bol, A.D. Franklin, D. Farmer, E. Kratschmer, K.A. Jenkins, W. Haensch, IBM T.J. Watson
Research Center]
Top: Graphene IC process flow. Bottom: Cross-sectional SEM micrograph of the post-CMP wafer showing the inverted-T gate structure.
Print
Email
Save
