October 28, 2011 - Two Wall Street analysts report their impressions from last week's EUV Symposium (Oct. 17-19 in Miami), where companies in the EUV supply chain reported their latest results and planned progress through 2012. And don't look now but there's a competition brewing in source power.
Chipmakers and suppliers have figured out tricks to keep pushing optical litho (193nm) and seem prepared to do so through the 2Xnm nodes using immersion (2nd-gen), multiple patterning (double, triple, or even more), and design-for-manufacturing techniques. But to stay on Moore's Law at 1Xnm and below, the industry needs EUV --and lack of acceptable progress is making chipmakers increasingly uneasy. First and foremost, throughput issues need to improve dramatically, which means primarily getting light sources up to snuff. (Other areas of EUV have been "largely resolved," from resists to reticles to optical quality.) Throughput is still in the low teens, and although ASML and partners have recast promises of ~60 wafers/hour by mid-2012 and 100WPH by end of next year (seen as the baseline for economically viable volume manufacturing), that's about a year and a half beyond original expectations, and there's mounting frustration at the progressive baby steps. "[The] "roadmap slip for EUV sources must stop," Barclays' CJ Muse quotes one BACUS attendee as saying.
A quick summary about 193nm litho vs. EUV, pulled together by Credit Suisse's Satya Kumar:
- Lithography technology represents about ~23% of current investments in wafer-fab equipment -- a number that will go up as devicemaking gets more complex (aka increased "capital intensity")
- Immersion litho systems cost $50M (€35M); their throughput is ~150-175WPH. (throughput will vary depending on schemes e.g. multiple patterning)
- EUV ASPs are nearly twice as expensive, ~$100M (€70M) or more -- but with only ~10WPH throughput today. (100WPH is the generally accepted level to support volume manufacturing)
Here's a slide from ASML (via Credit Suisse's Satya Kumar) showing essentially why chipmakers need EUV to happen:
Process flow comparison, 193nm with double-patterning vs. EUV. (Source: ASML, Credit Suisse estimates)
Following is a detailed summary of the EUV Symposium, incorporating observations by Barclay's CJ Muse and Credit Suisse's Satya Kumar, on both the EUV technologies and company updates:
ASML says it is building its first pilot system with the new NXE:3300 which is in final module integration stage, which offers higher NA to enable faster throughput. It is tripling production capacity for NXE:3300 tools in 2011, and still has 10 tools in backlog. A 150wph-capable NXE:3300C generation system is in the works to ship in 2013.
ASML is the default vendor when discussing leading-edge litho like EUV; "there is near zero market share risk with ASML on EUV for the next several years," notes Credit Suisse's Satya Kumar. Nevertheless, it's not the only litho vendor out there working on EUV. Nikon had a talk at the EUV Symposium about a new process to make the mirrors for EUV tools, he reports.
Cymer says it has built eight 1st-gen laser-produced plasma (LPP) sources ("HVM1"): four are installed and exposing wafers (Intel, Samsung, Toshiba, and suspected Korean memory maker i.e. Hynix), a fifth is being installed at TSMC, another is at ASML, and two more are at Cymer's own R&D labs. Current performance in the field is reported as 8W at 50% uptime, which translates to about 11WPH throughput. Cymer says it has demo'd 100W "burst power" for these first-gen sources. A forthcoming "Upgrade 1" coming in Dec. 2011 will boost exposure power to 20W, <0.5%>
The next Cymer sources ("HVM2") are slated for "first-light" in Feb. 2012. Two of these are being built for ASML; Cymer is procuring materials for four more (two for ASML, two for in-house), and has more orders for delivery through 2012-2013. Two upgrades are on the way: "2a" to reach 50W in 1Q12, and "2b" to top 100W in 2Q12. Ultimately Cymer's roadmap calls for future sources (HVM3 and HVM4) that will eventually top 500W.
Ushio, meanwhile, has been quietly making progress with its own EUV source, a laser-assisted discharge-produced plasma (DPP) technology (née Xtreme Technologies). Ushio claims it has demo'd 15W and 20W power levels at 100% duty cycle, and claims up to 37W at 50% duty cycle. A new upgrade will push input power to 48kW (translates to 50W laser power), but as a standalone module; a 300kW source for 250W output laser is in development, to be integrated with a NXE:3300 source. Ushio uses tin discs rotating through molten tin, creating a plasma assisted by a laser. Foils that keep tin droplets off the mirror are expected to last a year, vs. days/weeks for Cymer's mirror.
ASML appears to be taking notice of Ushio's progress as it now shows the company's data in its own presentations, Kumar points out. "It is now fair to say that Ushio is a valid competitor" with Cymer in EUV source power, he writes; "both appear neck and neck" in source performance. Only IMEC's EUV tool currently uses an Ushio source, but Kumar thinks it's only "a matter of time before ASML announces orders for Ushio light sources for R&D in its laboratories." Ushio claims fewer issues on paper, but that could be simply due to having fewer sources in the field from which to report problems, he adds.
Bottom-line comparison: Cymer's source is at 35W, 80% duty cycle, and 0.5% dose stability. Ushio has shown 30W at 90% duty cycle and 0.2% dose stability. (Duty cycle refers to how long the source emits light; 100% duty cycle would be continuous operation. Since litho steppers only expose some of the wafer at a time (up to 100 exposures/wafer), the laser isn't always on, limited by the scanning speed.)
Cymer also said collector lifetimes are increasing, too: 30B pulses by YE2011, doubling to 60B by 2Q12, again to 120B in 3Q12, and 260B by 4Q12. (Kumar calculates at 40kHz that 30B pulse limit will take about 8-9 days of continuous power.) Also improving is collector service (to 72hrs in 1Q12 and then 8hrs by 4Q12 and droplet generation targeting 21 days stability and ≥120 days runtime. Kumar notes that hiking the input CO2 power means creating more heat, and splattering of tin drops inside the chamber, which "will generally make all things more difficult to control."