August 12, 2011 -- Laurent Malier, CEO of Leti, described the research group's work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon (Si photonics), in a video interview at SEMICON West 2011.
Malier says performance data at 22nm shows FDSOI is comparable to FinFET with respect to the speed gain and low power performance. FDSOI technology is also easily manufactured and it's ready for scale down to 11nm, Malier notes.
Leti also recently demonstrated 3µm through silicon vias (TSV) for a via-middle application. Malier sees no major roadblocks to implement the technology, provided that the ecosystem to support 3D TSVs emerges on a global basis.
Integrated photonics on silicon is also making progress. The research group has demonstrated the major building blocks for silicon photonics basic functions. The next 2-3 years will be spent assembling them to do complex functions. Leti has been pressured by foundries to develop a standardized set of processes on 300mm wafers, Malier says.
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