July 1, 2011 - Researchers at IBM say they have developed a phase-change memory (PCM) that mitigates drift and demonstrates long-term retention of bits stored, with reliability far closer to what will be needed for enterprise applications.

The promise of PCM nonvolatile memory is speed and simplicity vs. flash -- PCM can write and retrieve data up to 100× faster than flash, but is more durable (at least 10M write cycles vs. flash's 30K for enterprise-class or 3K consumer-class). A PCM memory device recently built by a group of academia and industry (UC/San Diego, Micron, BEEcube, Xilinx) achieved read speeds of 327MB/sec and write speeds of 91MB/sec, 2×7× faster than a state-of-the-art, flash-based SSD. (In separate work, Leti says that N-doped GeTe can further boost PCM's data retention and switching rates.)

Four distinct resistance levels to store the bit combinations "00", "01" 10" and "11". An iterative "write" process -- applying voltage pulse based on deviation from desired level, measuring resistance, and applying more voltage pulse until the levels match -- helped overcome deviations in the resistance due to inherent variability in the memory cells and the phase-change materials, explained Haris Pozidis, manager of memory and probe technologies at IBM Research-Zurich, in a statement. A worst-case write latency of about 10μsec was obtained, a 100× performance increase over even the most advanced flash memory on the market today, the scientists noted.

For improvements in reading data, the scientists addressed the problem of short-term drift, which causes stored resistance levels to shift over time, causing read errors. (Reliable data retention is less of a problem in single-bit/cell PCM.) Resistance increases over time after the phase changes. To mitigate this problem, they applied a "drift-tolerant" modulation coding technique, which takes advantage of how the relative order of programmed cells with different resistance levels doesn't change due to drift.

The result: demo of drift mitigation and long-term data bit retention, in a 200,000 cell subarray of a PCM test chip, built on IBM's 90nm CMOS technology, designed and fabricated at IBM sites in Zurich and the US (Yorktown Heights, NY and Burlington, VT). The retention work has been ongoing for more than five months, which the researchers say indicates a level of reliability "suitable for practical applications."

A paper on the drift-tolerant multilevel PCM was recently presented at the 3rd IEEE International Memory Workshop in Monterey, CA.