3D transistor project wraps

February 7, 2011 -- Siltronic AG, silicon wafer producer and a division of Wacker Chemie AG, has completed its SIGMADT research project on silicon-based starting materials for three-dimensional transistors.

It was supported for a period of 30 months by a €3 million grant to Siltronic AG from Germany’s Federal Ministry of Education and Research (BMBF). The objective of this basic research was to optimally adapt the properties of silicon wafers to the requirements of future three-dimensional transistors. As integration density continues to increase in the future, it will become even more difficult to make electronic components for complex applications in nanoelectronics -- such as navigation systems or computer tomography equipment -- on just one plane. To achieve higher efficiencies and lower energy consumption, the transition to the third dimension is an important step. To meet these challenges, it is absolutely essential to improve the quality of the starting material -- which is the
wafer.

The development of an innovative mechanical planarization step was an important technological result in making a decisive improvement to the topological variation of the wafer surface. This nanotopology is a crucial product parameter for the planarization of dielectric layers. It bridges the gap between local flatness, which is of importance in lithography, and micro-defect density and roughness, which is important for surface quality. The new technology not only promises certain advantages for surface topology, it is also particularly environmentally compatible, since the only byproducts are silicon and water. Other technological challenges addressed included improvements to local flatness at the edges and in the planeness of the 300mm wafer, as well as a reduction of micro-defect density on the surface of the wafer.

The product properties are now approaching values that will allow the silicon starting material to be used in the production of critical component dimensions below 32nm. Upon completion of the project, Siltronic will integrate the processes and tools developed into a market-ready process chain at the Burghausen and Freiberg sites for large-scale production of silicon wafers for the latest generation of components.

Funded as part of the German federal government’s high-tech strategy, SIGMADT made it possible to collaborate early in a strategic research field, which included IHP GmbH -- Innovations for High Performance Microelectronics/Leibniz-Institut für innovative Mikroelektronik (Frankfurt/Oder), Semiconductor Technology Research (Erlangen), the Institute of Electrotechnology (Hanover) and NanoPhotonics AG (Mainz) as cooperating partners and subcontractors of Siltronic AG.

Siltronic provides hyperpure silicon wafers and partners with many top-tier chip manufacturers. Its production facilities in Europe, the USA, Asia and Japan develop and manufacture wafers with diameters of up to 300mm. To find out more, visit www.siltronic.com.

Subscribe to Solid State Technology/Advanced Packaging.

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi.

Or join our Facebook group

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.


VIDEOS

Electroiq 2 EIQ2

NEW PRODUCTS

Spectra-Physics introduces industrial picosecond laser

May 10, 2013 Spectra-Physics, a Newport Corporation brand, introduces Spirit ps 1040-10, an industrial-grade picosecond laser for precision ...

Multitest announces ecoAmp for high-power applications

May 8, 2013 Multitest announces that its ecoAmp high power Kelvin contactor successfully passed a challenging evaluation for an automotive ...

EV Group rolls out EVG120 processing system

May 7, 2013 EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, t...

Quartz Imaging introduces automated measurement for semiconductor images

April 30, 2013

It can be very time-consuming for engineers to measure the various features of an X-SEM image of a semiconductor device.


TECHNOLOGY PAPERS

Rapid Defect Indentification with Layout-Aware Diagnosis

Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are...

Flip Chip Devices get Flat and Happy

Thin is definitely in, but what our modern flip chip devices really want is to be flat and happy! As flip chip die have become increasingly thinner in recent...

WEBCASTS

Surface Cleaning and Preparation

This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL...

450mm Status Report

Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business...

SUBSCRIBE

LATEST ISSUE

05/01/2013
Volume 56, Issue 3

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS