This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

 Robert L. Rhoades, Entrepix, Inc., Tempe, AZ USA

January 11, 2011 -- The prevailing trends for 22nm integration strategies are towards strained layer channels and high-k metal gates in the front end with Cu (or possibly aluminum) and ultralow-k dielectrics in the back end. A relatively small number of device manufacturers are pursuing the 22nm node, and each will likely have a preferred approach requiring custom solutions at several unit operations in the flow. For cleaning chemistries or CMP consumables, this means products must either have very wide process margins, or better yet, allow tuning by the end user. The days of having a universal solution for all users at any given node appear to be over.

Alternate materials are being explored to help solve some of the difficult performance challenges that exist for 22nm design rules. Some may be simple extensions of integration lessons learned at 45 or 32nm, but some may require completely new materials options. For example, metal gates may include pure metals or nitrides; silicides or carbides of tungsten, tantalum, ruthenium, molybdenum, or other metals not yet published.

Since the patterning process will likely include CMP, slurries must be developed (or at least evaluated) across all of these materials. Post-CMP cleaning chemistries must also be optimized for cleaning without etching or roughening the exposed surfaces. A similar situation exists for metal interconnect layers with regard to the barrier metal under the Cu where ruthenium, cobalt, and several other metals are being evaluated along with extensions of the current favorite, tantalum. The permutations and interactions that need to be evaluated relative to CMP and cleans are significant.

In addition to the need for customization and flexibility, another dominating theme across all process modules is defect reduction. With such incredibly small features on the wafer, the particle size or surface imperfection that represents a killer defect is smaller than ever. To control potential defect sources, cleaning steps are being added at several levels, especially prior to photolithography. Previously acceptable amounts of surface topography are unacceptable at the 22nm node, with some layers requiring topography control better than 3nm. This leads to extremely tight process margins for CMP and etch; thus, run-to-run active feedback control is being increasingly pursued. Even seemingly simple processes such as wet cleans are being pushed to reduce wafer-to-wafer variation, which is causing many integration teams to move away from immersion baths and toward single-wafer cleans.

Combining the wide array of materials with narrowing process margins and an extreme focus on defects, the fabrication of 22nm devices will be a significant challenge for CMP and cleaning process steps.