(November 19, 2010) -- Christopher Bencher, member of the technical staff at Applied Materials, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on process and integration-based scaling for 15nm nodes. In an interview with Debra Vogler, senior technical editor, Bencher discussed the company’s development work at 15nm (Figure).
|Figure. 15nm half-pitch demonstration by sidewall spacer quad-patterning (SSQP). SOURCE: Applied Materials|
Two realities are driving the push to 15nm. As Bencher noted in his presentation, if NAND Flash memory stays on a two-year cycle, the industry will need 15nm-hp in pilot production by 2014. Additionally, if logic manufacturers adopt the FinFET, the industry may see 15nm-hp in logic 2014/2015. Bencher details the work being done to realize 15nm-hp. "Devices have a long design cycle...so you have to pick your patterning technique several years before that," observed Bencher. So Applied Materials is in the process of doing capability checks using a number of techniques that Bencher summarizes in the interview. Bencher reports that very good on-wafer results were obtained using 1) quad-patterning using conventional immersion, and 2) with double-patterning on EUV. He told ElectroIQ that both methods show concept and feasibility to meet the patterning requirements within the timeline for 15nm.
Bencher called self-assembly the new paradigm, and AMAT has been working on it for sub-15nm. Most of the technology is in the synthesis and design of the polymers, which is not Applied’s area of interest. However, it is interested in evaluating different polymer systems and how well they can be controlled to form circuit patterns. "This is an opportunity to break our dependence on optical lithography and combine optical lithography with chemical litho," said Bencher.
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