by James Montgomery, news editor
October 12, 2010 - A daylong series of presentations, facility tour, and one-on-one discussions at a recent SEMI-hosted seminar at the U. of Albany College of Nanoscale Science and Engineering (CNSE) spurred intense discussion about the state of leading-edge chipmaking technologies, including 3D ICs and new device structures, and why Wall Street and roadmaps are hampering true technology innovation.
Everyone's working on new devices, structures
With rising design costs and R&D costs vs. sales, it's a world of "bigger bets" as design starts taper off for all but higher-volume apps, noted David Bennett, VP of alliances for GlobalFoundries. But for those successful advanced technologies, the revenue payback climbs steeply at 4Xnm vs. 65nm, he said. Notably, GF is making such a bet with its forthcoming Fab 8 in nearby Malta, NY, which Bennett called the "critical mass" center of the company's manufacturing plans (while keeping "significant modules" in Dresden and Singapore).
|A day at Albany CNSE:|
|Leading-edge techs, innovation vs. efficiency|
|Mapping EUV's progress|
|Drilling down into packaging|
|Nanofab tour, future plans, and unearthing Washington|
CNSE also has work on III-V transistors, including figuring out how to incorporate magnetic tunnel junctions which are contaminants to silicon, as part of its "derivative development" for proof-of-concept technologies on an IBM flow, according to Michael Liehr, AVP for business/alliances/consortia at CNSE. He also described a broad collaboration among CNSE, SEMATECH, and the Semiconductor Research Corp. (SRC) in a range of areas, some with immediate impact (e.g. equipment infrastructure, metrology, process development) and others 10-20 years out (novel materials and device concepts, e.g. graphene-based). This includes CNSE's Center for Advanced Interconnect Science and Technology (CAIST) charged with developing interconnect technology down to 11nm (e.g. C4), a post-CMOS switch consortium, focused on processes and standards for using graphene around the 6-8nm generation, and a connectivity center (led by Georgia Tech) focused on <65nm "more than Moore" technologies, e.g. system-level 3D integration.
Included in discussion of new semiconductor technologies and structures is the next wafer size upon which to put them. ISMI continues to coordinate 450mm work; after initial testbed/prototype work in 2008 and metrology and process equipment development in 2009, final steps in 450mm development for 2010 and beyond show fewer, yet ultimately the most important, work: equipment prototypes, demonstrations, and equipment readiness.
Why roadmaps are hurting innovation
Peter Wright, research director at Tradition Equities, shone the light onto discussion of leading-edge technologies from a different angle: the potential drawbacks of a focus on efficiency and emphasis on development over research, including (and possibly exacerbated by) the adherence to an industry roadmap.
Wall Street and industry views don't see things the same way, he explained. Where the Street thinks optimistic metrics are risky divergence from average trends, the industry understands its usual inherent ebbs and flows -- e.g., higher capital spending is supported by more than a dozen new fab projects, but the Street wants to get out ahead of the next downward curve. The most recent cyclical upswing was longer and more pronounced than a typical upswing, say Street watchers, while to industry this is irrelevant since this is the first demand-driven cycle in a while. Record profits are unsustainable, says the Street -- but industry says profits will improve thanks to improved operational efficiencies. Wright showed a number of charts illustrating a sectorwide lack of enthusiasm from investors, even though fundamentals have outperformed, from growth to profits to capital intensity.
The real problem, Wright claims, is that manufacturing is the true source of innovation, but has been usurped by worship of efficiency, taken form as the industry's technology roadmap. Manufacturing is being driven by quarter-to-quarter economics and moving away from vertical integration, he said, but innovation is highly dependent upon integrated feedback, especially during manufacturing. Outsourcing and depending upon others' processes limits design optimization and makes second sourcing of manufacturing difficult -- e.g. a HKMG gate-first design is highly unlikely to be second-sourced to someone who uses a gate-last approach. (An audience member during the Q&A pointed out that the trap of being a foundry, even TSMC, is always being a fast follower. GlobalFoundries' Bartlett noted that advanced technology is driven by advanced designs, e.g. MPUs -- but zinged that he would not dispute that point regarding his Taiwanese competitor!)
And while industry roadmaps get everyone proverbially on the same page to pursue efficiently manufacturable technologies, this promotes the very standardization and consolidation that shuts out innovations (and investments) in disruptive technologies that drive sustainable industry growth, Wright argued. "The roadmap is the biggest hindrance to research," he stated. "R&D is becoming D." In the Q&A, David Bennett, VP of alliances for GlobalFoundries, offered that stifled innovation blamed on roadmaps is not necessarily a bad thing, but the trick is how to apply it to R&D. Roadmapping is essential to stay on the leading-edge of manufacturing, but "fewer companies are playing that game," added Michael Liehr, AVP for business/alliances/consortia at CNSE. The ITRS' vagueness in areas like 3D leaves room for innovation to happen, he added and opens up the field to more players with "no limit to creativity."
Wright suggested future sources of manufacturing innovation will be fleshed out from efforts to optimize the supply side of the industry: e.g. decreasing wafer lots vs. making bigger wafers, fab optimization vs. new fabs, reduced cycle times vs. squeezing the supply chain, and standardization vs. centralization -- and even economic savvy vs. pricing power (think ASML and lithography tools).