by Michael A. Fury, Techcet Group
June 14, 2010 - Day 2 of IITC 2010 started with a session on back-end memory and MEMS, with the emphasis on non-volatile candidates for storage-class memory. Greg Atwood of Numonyx described their 128Mb PCM product demo, which has 3 copper levels and has passed 108 memory cycles so far; volume production is expected to begin with a 1Gb device later this year. Cross-Point Memory, CMOx from Unity Semiconductor was described by Rene Meyer as a transistor-less four layer device with metal top and bottom electrodes, a "connective metal oxide" (a sputtered perovskite) and a sputtered high-k dielectric. The device provides analog storage function by field-induced migration of oxygen ions. Meyer asserts that NAND flash cannot be scaled to 10nm, as there would be only 4 electrons available for each state transition, whereas CMOx transitions would still involve 300 ions at that scale.
Shuntaro Machida of Hitachi presented a BEOL-integrated MEMS pressure sensor that eliminated traditional MEMS packaging issues and demonstrated an altitude sensitivity of 1m. The same design principles have been used to fabricate an ultrasonic transducer that is intended for medical imaging devices. Vikram Joshi of Cavendish Kinetics showed a BEOL-integrated MEMS mechanical switch that can be used to mimic logic functions with zero leakage current. With minor design variations, the same mechanism can be used for NV RAM or sensor devices.
The reliability and characterization session included a TEM method for characterizing Cu nanocrystal defects to 5nm, low-k damage using monoenergetic positron beams, and a model for the impact of LER on TDDB at 20nm half-pitch. F. Chen at IBM showed a 100× improvement in electromigration in 32nm Cu lines using a selective electroless CoWP metal cap with no TDDB or low-k leakage degradation.
The poster session included fourteen offerings that spanned the breadth of interconnect topics. Rob Rhoades of Entrepix needed to develop a Pt CMP process in order to implement a via-first Pt through-silicon vias (TSV) MEMS integration scheme compatible with a 700°C PZT anneal. Aleksandr Biberman of Columbia University stepped across the divide into optical interconnects, modeling the power performance of silicon photonic modulators for a full-scale on-chip optical interconnect network. The results show a critical deviation from the conventional wisdom of photonic networks-on-chip design, indicating that throughput optimization is not simply achieved with increased modulation rates, but requires a balance between physical and system-level performance metrics.
| SEE ALSO: |
| IITC Day 1: 3D/TSV, Cu barrier films, critical collaboration |
| IITC Day 0: Short course reflects interconnects' maturity |
The term "propeller head" has long been applied to techno-geeks of all sorts, but Chris Case, former CTO at BOC, has taken it to a new level. Chris has held his small craft pilot license for several years now, and has recently begun his certification to pilot helicopters. It's not known at this time if Chris will be able to wear his propeller-head beanie with his radio headset.
Security and confidentiality have always been issues in technical meetings of this sort, with engineers and scientists negotiating with managers regarding the details that can be released in external presentations. However, the semiconductor industry has seldom raised things to the level of the Healthsource Global meeting that took place in the adjacent conference hall, which had two armed guards posted at the door. It makes me appreciate that we all get along.
Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail mfury@techcet.com.
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