by James Montgomery, news editor
May 18, 2010 - In his Monday (May 17) presentation at The ConFab, Jim Clifford, SVP/GM of operations at Qualcomm CDMA Technologies, talked at length about the convergence of wireless connectivity and increasing performance requirements, the resulting technical (and economic) challenges brought upon supporting technologies, and the importance of "early engagement" to cost-effectively research and develop products.
Key highlights of his discussion:
|Jim Clifford, Qualcomm |
That also means increased demand for data usage, wireless features, and bandwidth requirements. In 1996, Intel's 80186 clocked in at ~2.5MHz and 10 millions of instructions per second (MIPS); by 2002 ARM's platform sported 146MHz/160 MIPS, and by 2006 had scaled up to 750MIPS, and spiked to 1.3GHz/2000+ MIPS by 2008 with dual-core custom CPUs -- and are on a 45-degree upward trend from here through the next few years, Clifford illustrated.
- Cost, power, and form factors will drive innovative technology scaling and "More than Moore" solutions. Twenty years ago, drivers for new product features, user experience, and look/feel were high performance and low cost. Today it's low power, low cost, form factor (small/thin) -- and still high performance. Take power for example -- battery capacity is "becoming a crisis," Clifford noted, as power requirements escalate beyond the scale of capacity.
The good news: the semiconductor industry is no stranger to challenges, it's faced plenty in the past two decades (six new process nodes, "red brick walls" moved back) -- invoking Gordon Moore's ISSCC 2003 talk, "forever has been delayed," and semiconductor economics have held together.
But it's not just technical challenges (e.g. new materials, structures, process options) that need to be figured out -- economic challenges also must be considered, e.g. increased capital and R&D costs, and fewer customers designing at the leading edge, which means a slower learning curve, Clifford pointed out. Cost-effectiveness has been an issue since the 90nm node, the beginning of a 29% cost/gate reduction for each node, and this can continue at 32nm/28nm only through process optimizations and accelerated DD reduction, he suggests -- e.g., with "careful DFM" and innovative packaging to reduce formfactors, such as through-silicon stacking, 3D stacked ICs, and stacked packages.
There are many challenges to be overcome, Clifford pointed out -- but if the semiconductor economics hold up, there will be many applications using it.
- Collaboration across the entire eco-system, and the "integrated fabless model." Speaking to Qualcomm's bread-and-butter, Clifford highlighted the "integrated fabless model" in which fabless companies engage with foundries very early on. In the IFM model, development starts toward the end of module development; then investing in IP/design/product development (including integration/qualification), and then production. An aligned ecosystem across the entire value chain (foundry, customers, research, EDA, IP, packaging, and testing) is required to optimize product innovation and execution. Clifford highlighted the need for early engagement with research organizations for a "co-design start," a phase dubbed "early pathfinding," which starts before and extends beyond module development and into integration/product development.
In the end, Clifford credited the IFM model for supporting Qualcomm's rapid rise to success -- it's the top fabless company in sales since 2008 ($6.5B/year), and is now No.6 in total semiconductor sales behind only Intel, Samsung, Toshiba, Texas Instruments, and STMicroelectronics, according to industry data (IC Insights and iSuppli). -- J.M.