by James Montgomery, News Editor, Solid State Technology
Jan. 23, 2008 - In an exclusive interview with WaferNEWS, Kurt Ronse, lithography program director at IMEC, discusses the newly announced partnership with the U. of Albany's College of Nanoscale Science and Engineering to accelerate development of extreme ultraviolet (EUV) lithography technology -- what finally pulled the two sides together, what they hope to gain short- and long-term, and plans for readiness by the 32nm and 22nm half-pitch nodes.
Widespread reports about the lack of progress in EUV development have not only fostered concern in the industry in general, but also within each consortia and the semiconductor industry companies working with them, Ronse noted. So, each consortia's members prodded them to work together to speed up the progress. (He added that SEMATECH's recent relocation of its headquarters to Albany along with much of its frontend manufacturing work did not have an impact on this burgeoning EUV partnership.)
Ronse explained the strategy of the IMEC-Albany collaboration boils down to making the most of the work needed with limited resources. There are only two EUV alpha tools out in the field, both requiring periodic upgrades (e.g. to power source levels, resists, mask technology). If one tool is down, that means work at that site stops. So, under the proposed collaboration, when one machine is unavailable for maintenance, progress in that group's programs can still be made using the other's EUV tool. IMEC's tool is now undergoing some upgrades, Ronse noted, so the group is shipping its wafers and reticles to Albany and is defining what work it needs to do. In coming months Albany also will undergo a tool upgrade, and that group will ship its wafers/reticles to IMEC, determine what exposures it wants, etc.
These work-swaps, while keeping IMEC's and Albany's individual programs progressing, also will help them establish a baseline to compare their initial EUV work, after nearly two years of informal discussions about what they've each been doing and comparing similarities/differences, Ronse noted. Witnessing results with both setups on both tools will help determine whether any differences are something fundamental to EUV itself, or whether there's something slightly different in each tool or in the resists/reticles, or even slight differences in operating procedures (ASML handles maintenance, but with two separate teams at IMEC and Albany). "We are definitely going to have a number of issues; some will be joint, others maybe on one tool only," Ronse explained. Exchanging info about their EUV work will let both sides learn faster.
As far as sharing joint results with customers, Ronse indicated that all the EUV results would be shared by each group's program participants -- which means that, for example, key Albany partners IBM and AMD would obtain the same data as IMEC partners Intel and TSMC, along with other participants in Europe (NXP, Qimonda), Korea (Samsung, Hynix), and Japan (Matsushita/Panasonic, Elpida).
Because of so many critical issues to overcome in EUV that have to be done in parallel and coordinated with ASML, Ronse noted, the IMEC-Albany collaboration is basing progress not on individual technology milestones, but in terms of technology nodes. Work with an eye toward 32nm half-pitch will continue over the next six months. But Ronse acknowledged that immersion and double-patterning are emerging as favorites at 32nm -- so by year's end, work will have shifted focus to requirements for 22nm half-pitch technology. "Development is probably never-stopping," he added. "There's not really a point where we say, 'and now source power is high enough,'" because constantly boosting source power increases throughput, and with improvements in resist and mask technologies, help keep lowering the total cost of EUV. "It's not an end, but to maturity, where research work is done," he said. Then it's "up to individual companies to develop something manufacturable. At that moment, work will migrate to the next technology node."