by M. David Levenson, Editor-in-Chief, Microlithography World
Double patterning technology (DPT), self-aligned or not, seemed to be the consensus choice for the next half-pitch node or two for the maskmakers convened in Monterey for SPIE's annual BACUS Symposium on Photomask Technology (Sept. 16-21) -- not that anyone thought it would be easy. The evident delay in EUV technology poses special challenges for the photomask community and these were highlighted in a special Friday session, sub-titled: "Twice the pain for twice the gain."
Artur Balaskinki of Cypress Semiconductor began the session by reviewing the results from the SPIE panel held in February: Double exposure double etch (DEDE) methods (where the pattern of one resist film is developed and transferred before a second film is applied, etc.) are expected to get to k1=0.18, which corresponds to 26nm half-pitch with water immersion. Self-aligned spacer/trim (SAS/T) methods (where a deposition step coats a sacrificial spacer pattern with a hard mask, subsequently trimmed, etc.) are projected to approach k1=0.13 (19nm hp), both well below the single-resist k1=0.25 limit. In spite of the evident difficulties -- litho CDU specs below 3.5% and overlay at 7% for DEDE but up to 20% for SAS/T, etc. -- February's expert panel predicted that the NAND manufacturers (at least) would do it.
Don Samuels of IBM introduced the litho-user's perspective by countering that DPT was a last resort, being developed in IBM alliances for prototyping, but not necessarily for production. However, the very restricted design rules required for a product to be built using DPT pointed toward improved yield with less exotic techniques. Methods devised for alternating phase shift mask designs were being re-applied.
Robert Bigwood of Intel observed that the DfM strategies that had to be implemented for DPT were not disruptive and need not lead to a great increase in time-to-silicon, especially if tasks were done in parallel. However, the mask data prep volume was going to be larger. Luigi Capodieci of AMD noted that there was a trade-off between process complexity and material sophistication. For example, a practical nonlinear resist or CEL could make the second coat and etch steps of DEDE unnecessary. Even so, materials companies are not actively seeking materials that would facilitate DPT, even simple ones like negative 193nm resist.
Mircea Dusa of ASML pointed out that DPT would be a challenge to the entire production system, not just lithography. In particular, etch bias would be a major CDU contributor and metrology needed to be improved -- quickly. He suggested that metrology tools could be used for compensation, not just dispositioning, so that anomalies like a reticle CD fingerprint on one exposure could be compensated in the second using a pre-distorted dose profile, for one example. Dedicated tools might be needed, though, both for exposure and metrology, ending "mix-and-match."
Dusa also presented a paper from Mireille Maenhoudt of IMEC that sketched numerous double patterning options, from "freezing" the first resist pattern (thereby reducing the number of hard masks needed) to double development, where the highly exposed regions of resist dissolve in a positive-tone developer while unexposed regions are removed in a negative-tone developer, leaving a grating with half the exposed pitch. It remains to be proved that all the CDs can be controlled sufficiently to yield working circuits, but the proof-of-principle experiments have been done, he said.
Speakers from EDA companies Cadence and Mentor Graphics emphasized that DPT litho tools must be embedded in today's designer flows, without disruption -- fabless companies are fabless because they don't want to know manufacturing details, even crucial ones. Nevertheless, there is a successful example of design interfacing with sophisticated manufacturing models: RET.
Maskmakers and tool vendors seemed remarkably sanguine about DPT, perhaps because to the possibility for increasing volume. Takihashi Kamikubo of Nuflare, the dominant manufacturer of e-beam write tools, pointed out that scanner alignment errors dominated mask effects. The low stress mask blanks and charge dissipation layers thought to be needed to meet the demands of double patterning already exist. Bill Broadbent of KLA-Tencor claimed that their 600 series defect detection tools would meet the "basic requirements" of 32nm DPT masks in 2009. However, he did note that the company offers no placement metrology tools, and the 600 would not detect the displacement of an entire region of a plate. Jun Wei Bao of Timbre Technologies suggested that a scatterometry-based methods would soon be achieve sufficient overlay and CD sensitivity for 32nm DPT.
Han-ku Cho described the present state of the art of DPT achieved by Samsung, which does not expect any other litho solutions to be available by 2009. He pointed out that the scanner stage randomness consumed 60% of the error budget in dede DPT, motivating SAS/T techniques, and asked for accelerated development of an image placement metrology tool sufficient to fulfill the DPT registration specs.
Images of hamburgers with one, two, and four patties were served up by DNP Fellow Naoya Hayashi to illustrate the challenges of multiple patterning lithography. Overlay becomes more challenging as the number increases, but DfM restrictions are reduced because more geometries can be separated without conflict when the mask set is larger. Because of manufacturing efficiencies and quality trade-offs, the cost of a DPT mask set would only be 1.7X that of a comparable single mask, not 2X -- just as a double hamburger does not cost twice as much as a single patty, he explained.
Franklin Kalk of Toppan Photomasks concluded the usually dour mask-making symposium with a remarkably optimistic view: It is all do-able! He claimed that the "random" placement errors characteristic of certain e-beam mask writing tools are not random at all, but correctable systematics related to the position of the beam in the physical lens aperture, which is not presently modeled or measured. So while tool development is necessary, it is not impossible to understand and correct the errors with the most impact. In addition, when 32nm logic actually has a minimum pitch of 90nm, Kalk claimed it is possible to meet the 5nm overlay spec by selecting the best masks from current production. Even a 1nm CD spec is doable if all of the improvements that maskmakers know about -- but have found uneconomical to apply -- are actually implemented, he predicted. Kalk also mentioned that he had just recovered from the bite of a mysterious spider and was looking forward to new adventures. -- M.D.L.