by Ed Korczynski, Senior Technical Editor

Mobility enhancements in ICs have typically been implemented using strain and mostly the same materials, but the industry is now working with high-k dielectrics and metal-gates (HK+MG). Keeping the same leakage levels, going from poly to metal-gate allows for equivalent oxide thickness (EOT) reduction of ~2Å. Applied Materials has released an ALD for hafnium-oxide HK dielectric chamber for the Centura platform that appears to be part of an excellent integrated HK+MG solution. "Integration is critical, since you need almost 15 layers to make this work," explained Reza Arghavani, in an exclusive interview with WaferNEWS.

A "gate-first" process flow—officially undeclared yet widely understood to be used by IBM—requires some tuning of the dielectric to separately optimize for nFETs and pFETs. Certain "cap oxides" when deposited over hafnium oxide form dipoles in the vertical dimension, so the gate-first process flows are sometimes termed "dipole" dielectrics. "You touch it up with either lanthanum oxide or aluminum oxide," explained Arghavani. "IBM has shown this. Applied Materials didn't invent it, but is bringing it to volume manufacturing."

A "gate-last" or "replacement gate" process flow is officially undeclared yet commonly understood to be used by Intel. Such a process flow is nearly identical to FUSI up to the point of silicidation, where a poly trench etch opens the space replacement with dual metals. Applied Materials proposes ALD on top of a PVD seed for these critical metal depositions. (Incidentally, "FUSI and MAP are finished," Arghavani informs. "There is no customer who is interested in FUSI for 45nm.")

The Centura platform has been providing a four-chamber solution to optimize the SiON formation since the 180nm node, including tuning the nitrogen gradient within the stack. Since the HK portion of a gate dielectric stack still requires some SiON as an interface to the silicon channel (see figure), the new integrated process uses RadOx (oxidation), DNP (nitridization), ALD, and annealing chambers.

TANOS (tantalum, alumina, nitride, oxide, silicon) FLASH memory structures may be the next major application for integrated ALD after logic gates. "Both Toshiba and Samsung have said that they want to go to 'charge-trap' structure," commented Arghavani. --E.K.