Nov. 18, 2002--San Jose, CA--Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Cadence Design Systems Inc. have collaborated to solve design challenges in 130 and 90nm process technology signal integrity (SI) closure.
As a result, TSMC has qualified the Cadence tool suite for inclusion in its next-generation TSMC Reference Flow.
TSMC's Reference Flow 4.0 will incorporate the Cadence Encounter system from virtual prototyping to physical implementation. This complete system will enable designers to account for SI effects early in the design process, and to make systematic, predictable progress toward SI sign-off, according to the companies.
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