X-wafers printed

05/31/2002

By: M. David Levenson
WaferNews Technical Editor

In another step towards freeing chip architects from the tyranny of Manhattan geometries, The X Initiative and ASML have announced the first 0.25-micron diagonal features printed on wafers. An ASML PAS 5500/750 DUV step-and-scan tool equipped for annular illumination successfully patterned diagonally oriented interconnect structures characteristic of 0.18-micron node design rules.

These proof of concept results indicate that the X-architecture implemented by Simplex Solutions and fabricated on reticles by Dai Nippon Printing can be used to pattern interconnect layers. The wafer results also validated lithography simulations obtained with ASML MaskTool's LithoCruiser software. Risto Puhakka, of VLSI Research, observed that, "The results of ASML's experiments using current-generation equipment demonstrate that X-architecture designs are both production-worthy and manufacturable."

Jan Willis, the X Initiative steering group coordinator, pointed out that ASML's participation increased the number of participating companies to 33 and demonstrated solidifying supply-chain adoption. While the X Initiative has been portrayed as using diagonal lines at metal 4 and 5 (in orthogonal directions), obtaining the full benefit requires the "liquid routing" innovation, which allows a combination of x-y and diagonal orientations for every connection on metal layer 2 and above as required. Toshiba has shown that this freedom reduces both the wire length and the number of vias on a chip design. Until today, a question remained whether one could print and inspect the resulting irregular wafer patterns.

Adolph Hunter of ASML pointed out that the X-Wafers showed no difference in lithographic process window compared to Manhattan designs at the same dimension. Reticles patterned with both raster-scanned laser and vector-scanned e-beam technologies showed the same performance for printing dense and isolated features at 0.25-micron. Since the X-architecture has been shown compatible with existing reticle and exposure tool technology, future implementation steps should prove less challenging than past innovations, according to Kenneth Rygler of Rygler and Associates.

WaferNews

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. 


VIDEOS

Electroiq 2 EIQ2

TECHNOLOGY PAPERS

Automated Test Creation for Mixed Signal IP using IJTAG

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis

This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...

WEBCASTS

3D and 2.5D Integration: A Status Report Live Event

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

Oh, snap!: Pics from The ConFab

Sun Jun 03 19:09:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

Volume 56, Issue 1

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS