The templates needed for 1× step-and-flash imprint lithography can be fabricated using extensions of current optical mask manufacturing technology.
Douglas J. Resnick, Ecron Thompson, L. Jeff Myron, Gerard M. Schmid, Molecular Imprints Inc., Austin, Texas
Over the last 30 years, many different varieties of next generation lithography (NGL) have been proposed as successors to optical lithography, but the continued extension of that technology - combined with the lack of a commercial NGL mask infrastructure - made it extremely difficult for any NGL to penetrate the silicon market. How will imprint lithography avoid sharing the fate of the others?
Imprint lithography has now been included on the ITRS lithography roadmap at the 32 and 22nm nodes . Step-and-flash imprint lithography (S-FIL) is a unique method for printing sub-100nm geometries [2-4]. Relative to other imprinting processes, S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. S-FIL provides sub-100nm feature resolution fairly inexpensively, compared even to optical lithography, and avoids some line edge roughness phenomena. However, since imprint technology does not reduce dimensions, it is critical to address the infrastructure associated with the fabrication of 1× templates.
The S-FIL blank has an advantage over those for x-ray, EUV and particle beam lithography, in that the starting material is essentially identical to what is being used in mask shops today. Although patterning at 1× dimensions is challenging, today’s 4× optical proximity correction (OPC) designs require features almost as small. Writing time may also be less at 1×, because of the reduced writing area and the elimination of OPC.
The template fabrication sequence is very similar to the chromeless phase shift mask (PSM) process currently used in mask shops. Four 1× templates are fabricated on a standard fused silica quartz 6025 blank (6" × 6" × 0.25") with a 15nm chromium layer. The processing sequence is depicted schematically in Figure 1. A standard positive tone resist is coated and exposed using an e-beam pattern generator. The patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as an etch block for the fused silica.
Figure 1. Template fabrication process flow.
In both the Cr-less PSM and S-FIL template route, the second level lithography step is exposed using a fast optical writer, such as an Alta 3700 laser pattern generator. However, in the case of an S-FIL template, the undeveloped resist must protect the entire active area while the 15μm high mesa is formed by wet etching the nonactive areas. The final step in the template process is a dice and polish step used to separate the plate into four distinct templates.
Of course, inspection and repair steps are also required. Although defects as small as 70nm have been detected using optical inspection , it is clear that electron beam inspection techniques will be necessary. Several technologies available today for repairing photomasks are also applicable to S-FIL templates.
Research and development templates, exposed with high resolution (but slow) Gaussian-beam writers have been fabricated with features as small as 10nm. Early work was done by Motorola Labs, using a Leica VB6 pattern generator operating at 100 kV . ZEP-520A, a positive chain-scission-type resist, was shown to have adequate resolution for 30nm features. While a variety of developers  have been used, a 50:50 mix of MIBK and IPA seemed optimal because it combines good resolution and minimum swelling. After exposure and development of the resist, the pattern transfer process for templates consists of an oxygen de-scum, Cr etch, resist strip, quartz etch, and a Cr wet etch.
Penetration of the semiconductor market depends on the availability of suitable shaped-beam template writers, which operate faster and can provide good image placement. Several commercial mask shops now accept orders for 1× templates written this way, employing chemically amplified resists to meet throughput requirements. Since only 1/16th of the area must be written (relative to a 4× photomask pattern), it is reasonable to relax the resist sensitivity somewhat (perhaps from 10μC/cm2 to 25μC/cm2) in order to improve line-edge fidelity following exposure and development.
Figure 2. a) and b) 70nm metal-1 template patterns; and c) 70nm logic template patterns.
Imprints of templates from three different mask shops for logic and metal-1 patterns are shown in Fig. 2. Both DNP and Toppan Photomask achieved 70nm resolution for the metal-1 patterns. IMS Chips (Stuttgart, Germany) resolved the more dense logic patterns at 70nm, and has recently demonstrated reasonably good resolution at 60nm for the metal-1 features. The high resolution required of 1× templates is accompanied by stringent image placement tolerances. Recent work at Photronics has demonstrated that it is possible to achieve 6nm, 3σ image placement within a 25 × 25mm template field using a Nuflare 4500 pattern generator.
To achieve patterns with even smaller dimensions, process development and device prototyping requires 100kV Gaussian pattern generators. Although these systems cannot meet the throughput and image placement requirements, they do provide an immediate path for fabricating templates for both process development and device prototyping. Imprint examples of 40nm half pitch DRAM contact arrays and 40nm metal-1 imprints are shown in Figs. 3a and 3b. To achieve 32nm resolution may require resist thinner than 100nm and proximity correction algorithms. Figure 3c depicts a ZEP520A resist image of a 32nm metal-1 pattern after the proper dose corrections have been implemented. The etch processes necessary to transfer the resist image into the fused silica template are being developed.
Figure 3. a) 41nm half pitch DRAM contacts, b) 40nm metal-1, and c) 32nm metal-1 e-beam patterned resist features for template manufacture.
Early work on fused silica templates with programmed defects established the feasibility for using DUV inspection tools in reflection mode . Reflection mode provided better contrast, and a KLA-Tencor 526 tool was capable of resolving defects as small as 70nm. However, there is clearly a need to detect defects much smaller than 70nm. E-beam inspection provides a potential solution, as long as the template is capable of dissipating charge. One way to do this would be incorporating a conductive and transparent layer of indium tin oxide (ITO) within the template blank  for the process shown in Fig. 4.
Figure 4. Patterning scheme for a conductive template. The upper SiO2 layer is deposited by CVD.
Electron beam inspection work by Hess and Nordquist established that programmed defects patterned on an ITO-based template can be calibrated in a CD SEM and inspected on a prototype e-beam inspection system, the KLA-Tencor eS30m . The initial images in Fig. 5 (left) confirmed that these ITO templates were inspectable; the contrast was acceptable and surface charging did not seem to be an issue with ITO. A second alternative is to perform the e-beam inspection on an imprinted wafer, and compare the imprinted patterns to a database. NanoGeometry Research Inc. has a suitable die-to-database inspection system, the NGR2100 . The system operates in a step-and-repeat mode by scanning the entire printed die pixel by pixel, essentially collecting CD information across the entire die at a 200MHz rate. The information is then compared to a reference geometry in the database and a series of algorithms determine whether a defect is present.
Figure 5. E-beam inspection picture of a 400nm pattern made on an indium tin oxide (ITO) template (left). The images to the right depict a CD SEM image of a 13nm programmed line edge defect on a 70nm test cell.
Initial experiments with the NGR2100 inspection tool were performed on imprinted wafers consisting of arrays of 300nm contacts and metal -1 patterns. Figure 6a depicts the detection of a 24nm intrusion on a metal-1 type feature. The same tool has also been used to detect 20nm defects in 70nm logic and metal-1 patterns printed using S-FIL as in Figs. 6b and 6c.
Figure 6. a) 24nm defect on a metal-1 pattern detected by e-beam inspection of an imprinted wafer; and b) and c) defects detected on an imprinted logic pattern.
Because the template fabrication process includes etching of both chromium and fused silica, the same tools that are used to repair photomasks can also be employed to repair templates. The earliest work on this subject was a collaboration on using programmed defects between Motorola Labs and RaveLLC . Repairs were conducted directly on the fused silica features using a RAVEnm 650 nanomachining system that comprises a proprietary nanomachining head on an AFM platform. Coordinates imported from an inspection tool can be used to drive the stage to a defect. High-NA optics are then used to image the area in which the defect resides. Finally, the AFM platform is used to image the defect and repair it. The subtractive repair system removed protrusions 300nm in size and trenches down to 50nm were cut in raised silica features.
Figure 7. Additive repair of a 200nm fused silica defect.
Additive repair is more difficult on fused silica. Any material added to the template must adhere to the glass, be transparent to UV, and also be compatible with the release layer applied to the template prior to imprinting. Carl Zeiss and NaWoTec have introduced the MeRit MG electron beam-based mask repair tool that is capable of both subtractive and additive repairs. The tool is based on a field-emission SEM, which is used to focus a fine electron beam at the point of interest and fragment a precursor gas resulting in very precise deposition (or etching) of material. An example of an initial attempt of localized oxide deposition is depicted in Fig. 7. Repair of a 200nm fused silica notch  results in a line edge that is matched well with the existing structure. Feature height is slightly mismatched, but these results are promising considering that this was a first attempt at repairing this structure.
Great progress has recently been made in template fabrication for imprint lithography. Commercial mask shops are accepting orders for templates and have shown an ability to pattern dense structures as small as 70nm. Die-to-database electron beam inspection technology appears promising, as do the repair technologies that are also used for photomasks. Clearly, not all the pieces are in place. Throughput remains an issue for patterning, inspection and repair. Note, however, that S-FIL represents a multigenerational lithography solution. As long as the template can be fabricated, images can be printed. A continued focus on template infrastructure for 32nm might facilitate a solution that can extend to the 22nm node and beyond.
The authors gratefully acknowledge the many contributions of the scientists and engineers from Motorola Labs, KLA-Tencor, DNP, Toppan Photomask, IMS Chips, Photronics, LBNL, NGR, RaveLLC, Leica Microsystems, and NaWoTec. This work was partially supported by DARPA and NIST-ATP. S-FIL is a trademark of Molecular Imprints Inc and MeRit is a trademark of NaWoTec.
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Doug Resnick is VP, template technology, for Molecular Imprints Inc., 1807C West Braker Lane, Austin, TX 78758; ph 512/339-7760 ext 332, e-mail email@example.com. Also at MII are L. Jeff Myron, who is developing the emerging infrastructure for NIL templates; Ecron Thompson, who is developing advanced template technology infrastructure; and Gerard M. Schmid, who is developing high-resolution templates and templates containing 3D structures.