Lithography for 300mm wafer-level packaging (WLP) is quite different from that for other applications. The packaging process is extremely cost-sensitive and requires nearly perfect yield with very thick photoresist and photopolymer layers. We will review technical advances of 1× full-field proximity mask aligners allowing cost-effective WLP lithography.
Wafer-level packaging (WLP) and wafer bumping technologies are very important for the performance of modern ICs. These backend or packaging technologies require a lithographic system quite different from that used in the frontend. WLP has become even more important for 300mm wafers, since it allows the economies of wafer-scale processing to be extended to packaging.
Packaging continues to be the most cost-sensitive aspect of chip manufacturing. It is therefore important for integrated device manufacturers (IDM) and packaging service providers to have access to cost-effective process technology that meets the specific performance requirements of WLP. There are three main types of layers involved in WLP: redistribution layers (RDL), which reroute on-chip perimeter pads to the array for the package I/Os; passive components (inductors, capacitors, resistors) integrated on chip; and bump (solder, gold, copper stud). There are two more layers, which are typically frontend that are now part of WLP — namely pad opening and stress buffer layer.
The minimum feature size in gold bumping or redistribution layers is typically around 10µm and will shrink down to 5µm for advanced LCD drivers and RDL traces in some wafer-level packages. Resist thickness, on the other hand, ranges from 20µm to >100µm for wafer bumping and up to 20µm for RDL.
Unit magnification (1×) exposure tools have been the standard for WLP lithography steps. Specifically, 1× full-field lithography (1XFFL) is the dominant technology used for packaging  300mm and smaller wafers due to the simplicity of full-field proximity mask aligners. This paper reviews the four critical lithographic areas for WLP and the 300mm technology enhancements comparing various 1× lithography approaches, with respect to cost-of-ownership (CoO) and technical capability. The lithographic approaches include 1× scanner, 1× stepper, and 1× proximity.
In modern packaging lithography, there are four main issues:
- Resolution (over an extended depth of field). In packaging, the layers of photo materials (resists, BCB/cyclotene, polyimide, etc.) are very deep. Layer thicknesses from 20 to >100µm are common. High aspect-ratio patterns are required for fine-pitch applications such as gold bumping.
- Overlay accuracy. WLP used on large-diameter wafers requires accurate mask-to-wafer alignment. Typical run-out specifications are near 1µm, which is 3ppm for a 300mm wafer.
- Wafer throughput. In order to keep CoO at a minimum, high wafer throughput is critical.
- High yield. Because WLP is at the end of the production cycle, the investment in the patterned wafer is very high. Yield loss of good chips during packaging is especially intolerable. At a minimum, WLP yield must be comparable to that of conventional packaging.
Resolution and thick-resist processing
Nowhere else in the wafer process does the resist thickness approach that found in WLP. The typical frontend lithography process uses submicron coatings. Packaging lithography starts with resist thickness >10µm and goes up to >100µm. How can optical patterns be printed in such thick films? The imaging system must be designed to have an exceptional depth of field. Consequently, the illumination systems must have a low numerical aperture or a high degree of collimation to image in such thick films.
Figure 1. Impact of exposure wavelength on sidewall angle for 12µm-thick Clariant AZ9260 resist exposed with a) g-, h-, and i-line illumination; and b) with g-line only, using a 30µm proximity gap and processed identically.
The exposure wavelength can also have a significant impact on sidewall angle. Figure 1 compares images in the same 12µm-thick film printed with two different illumination spectra. Monochromatic g-line illumination produced sidewall angles >85°, whereas broadband illumination gave <75°. In most cases, changing the spectrum requires replacing only one filter for 1× imaging systems. Figure 2 demonstrates that 1XFFL can image superthick-resist films; in this example, the thickness is 300µm. 1XFFL also can pattern resist covering severe topography, up to 300µm high (Fig. 2b.)
Overlay using temperature control technology
Overlay requirements for packaging are at least an order of magnitude reduced compared to the frontend process. However reduced the requirement, the user still needs to understand and control the various items that can impact overlay, with temperature control being one of the most important. One important concern for full-field lithography in WLP is mask-to-wafer overlay accuracy. High-end mask aligners that use optical microscopes in conjunction with pattern recognition systems can repeatedly align masks to 300mm wafers with ±1µm (3σ) accuracy. The three main reasons for potential overlay inaccuracies for all exposure approaches are:
- thermal run-out due to increased mask temperature,
- run-out due to an incorrect scaling factor for the photomask or wrong mask design data, and
- poor overlay due to prior process steps (orthogonality error from the frontend process, etc.).
Figure 2. a) 300µm of SU-8 exposed using the Süss 1XFFL; and b) exposed features in 6µm of AZ9260 resist over 300µm trenches etched into a silicon wafer, showing good depth of field.
Thermal run-out is proportional to differences in the coefficient of thermal expansion (CTE) between the glass mask and wafer (e.g., silicon). These thermal run-out effects become more obvious with increasing wafer size. Because of the cost sensitivity of WLP production lines, soda-lime glass masks have replaced fused quartz in the industry whenever possible. Soda lime has a CTE of 9.3×10-6/°C vs. fused quartz at 0.5×10-6/°C. In comparison, the CTE of silicon wafers is 2.3×10-6/°C, matching neither of the other materials. To compensate for potential thermal run-out between photomask and wafer (especially with large exposure doses), we have implemented and evaluated a temperature control system.
The ThermAlign temperature control system used by Süss MicroTec maintains a constant temperature on the wafer chuck during the entire process. The temperature of the water flowing through the wafer chuck is controlled by a computer, which senses the chuck temperature with a thermocouple. Due to the close proximity between wafer and photomask on full-field proximity systems, the mask temperature, in turn, also remains constant through many exposures.
High exposure doses cause the greatest temperature excursions and, thus, the most run-out. A high-dose process was chosen to verify the capability of the ThermAlign chuck: The most typical gold bump resist was used — the PMER PLA900 from Tokyo Ohka — and 100 200mm wafers were exposed at a dose of 3000mJ each (exposure at 30mW/cm2 g-line intensity for 100 sec). The run-out was measured by the auto-alignment system of the mask aligner and is depicted in Fig. 3 with and without the ThermAlign option .
With ThermAlign on, the run-out for all 100 wafers stayed below 1µm, which is satisfactory for WLP. Further optimization and elimination of the remaining constant alignment offset appears feasible. Without the ThermAlign chuck, however, run-out increased to 5µm after 100 prints as the thermal loading of exposure heated the reticle. This was an extreme case with very long exposure times. In most 200mm production environments, the thermal run-out remains smaller; however, the capability to control run-out in this way is crucial for 300mm processes.
Run-out caused by scaling-factor inconsistency of the photomask remains constant from wafer to wafer, but increases from the center to the edge of the wafer. This run-out component can be controlled by maintaining a specific maskwriting temperature or by compensating the mask data for temperature shift between maskwriting and mask usage. Mask design errors must also be avoided, which may require re-measurement of the processed wafer prior to packaging-mask design. These procedures are well understood by experienced mask suppliers and do not typically cause any issues in manufacturing.
Alignment offsets caused by previous process steps such as orthogonality error are not usually significant in WLP. These errors can be compensated for in full-field lithography by matching the WLP mask pattern to the underlying stepper fingerprint on the wafer. The process used is very similar to that used to match steppers to one another in facilitating global alignment. The pattern placement data collected from stepper matching can be used in WLP maskwriting.
The efficiency and economy of full-field lithography is most apparent when comparing throughput at 300mm with a stepper that exposes the wafer in segments. The comparison demonstrates the dramatic impact the number of exposure shots has on throughput, effectively comparing a single-shot exposure technology to a multiple-shot approach. Typical overhead times such as wafer load, unload, pre-alignment, and active/.global alignment systems are very similar for both exposure systems. Full wafer exposure has three main advantages, however: elimination of overhead associated with die-to-die stepping, higher-power lamp illumination generating higher time-average exposure intensities, and a low local-exposure intensity due to the fact that the radiation is spread across the entire wafer.
The details of the comparison are listed in Table 1. Although the "published" intensity is lower for a full-field exposure strategy, it results in a higher illumination when normalized to the same single-field exposure area. The overall impact on throughput at different resist exposure thresholds can be seen in Fig. 4. The higher throughput, combined with a tool cost up to 50% lower than alternatives, translate directly into lower CoO.
Figure 4. Comparison of throughput for different 1× lithography approaches as a function of the dose required for photoprocessing.
Some photoactive materials do not work well when exposed to high-intensity radiation for short periods of time. Specifically, diazo/novolak resist systems release nitrogen upon exposure , potentially causing yield loss due to "popping" or delamination of the resist from the wafer. Other materials may show reciprocity failure, in which higher-intensity exposures also require more dose. The mask aligner mitigates these problems by exposing the whole wafer simultaneously at a lower intensity, thus allowing more time for any gas generated to diffuse and potentially reducing total dose.
1XFFL, 1× scanner, and 1× stepper lithography  can meet the technology demands of WLP. Resolution, overlay, and resulting yield are not issues, but there are unique challenges, especially for 300mm wafers. They relate to process integration in the entire WLP sequence and they influence certain aspects of the lithography process downstream. Leading-edge WLP requires electroplating, which in turn requires specific, high-precision pattern placements on the edge of the wafer. Additionally, the thicker, wider resist-edge bead on a 300mm wafer must be dealt with to prevent problems caused by particles from wafer handling, wafer clamping, etc.
Lithography tools are often used to expose the wafer edge to remove the resist. This process works well for positive-tone photosensitive materials; however, negative-tone materials are important for WLP. Many of these materials have better overall properties when resist thicknesses exceed several microns. For example, photosensitive BCB from Dow Chemical Co. is an excellent permanent dielectric material with a low dielectric constant and good adhesion to itself and other materials, but it is a negative-tone material. Ideal negative-tone processing requires that the edge of the wafer be excluded from exposure. Furthermore, the positioning of the exclusion area needs to be very precise in order to prevent cutting off portions of die at the wafer edge resulting in die loss. Table 2 compares the two most common technologies for protecting the wafer edge from exposure. The photomask used in full-field exposure (and 1× scanning) provides a natural means for precise edge exclusion without potential wafer contamination.
WLP and wafer bumping applications often require lithography systems to define bump-array patterns across the wafer or to create redistribution layers or integrated passive devices. These backend lithography requirements are different from traditional microlithography. Typically, the resist layers are thick (20–100µm) and feature sizes large (3–150µm). Technical advances in temperature control, pellicle use , and system optimization have increased the capability of modern full-field lithography beyond these requirements.
The additional economy of scale for 300mm wafers makes WLP a preferred solution to wire bonding, yet backend processes are cost-sensitive and delicate as they process valuable product wafers, while 300mm stepper-based lithography costs are prohibitive. The use of 1XFFL systems is a cost-effective way to meet these process requirements. Over many decades, proximity mask aligners have shown low cost and reliability and now have a noticeable throughput advantage, making them suited for WLP/wafer-bumping lithography.
The authors would like to thank Clif Hamel (Süss MicroTec) for his support in carrying out experiments, compiling data, and conducting analysis. ThermAlign is a registered trademark of Süss MicroTec Inc.; www.suss.com.
- Cheang, Staud, Newman, "A Low Cost Lithography Process for Flip-Chip Applications in Advanced Packaging," Advanced Manufacturing Technology Seminar, 1997.
- Unpublished report: F. Runkel, Applications Center Europe, Süss MicroTec Lithography GmbH, Munich, Germany.
- Flack, Nguyen, Capsuto, "Characterization of an Ultra-Thick Positive Photoresist for Electroplating Applications," Proc. SPIE 5039, pp. 1257–1271, 2003.
- B. Levine, "Steppers Battle Aligners for the Hearts and Cash of Wafer-Bumping Providers," Chip Scale Review, July 2003.
- Mancini, et al., US Patent No. 6,300,042 B1, Oct. 9, 2001.
For more information, contact James Hermanowski, director of marketing at Süss MicroTec Inc., 228 Suss Dr., Waterbury Center, VT 05677; ph 802/244-5181, fax 802/244-5103, e-mail email@example.com.