BY STEVE WATKIN, NEIL SHORT, and CLIVE ASHMORE, DEK International
Demand for continuous reductions in semiconductor package height are coming from several directions, most notably memory chip vendors seeking increased density to meet aggressive price-performance roadmaps. Portable memory technologies are calling for memory ICs displaying a total profile of 1.0 mm and below. Pressure in world DRAM markets is driving the adoption of stacked-die devices that combine multiple die into surface-mount package formats that are already established, such as fine-pitch BGA.
At all package levels, new technologies, such as thin-core substrates and wafer back-grinding, are helping to meet the latest package profile targets, reducing wafer thickness to around 100 µm. To accompany these advances, coating processes performed at the wafer level (Figure 1) must also improve to deliver savings in bondline thickness. These include coating with epoxy underfill or die-attach adhesives, materials for wafer back-side protection, or a wafer bonding medium such as a B-stage epoxy or glass frit. After curing, a typical requirement on wafer B-stage epoxy coating is a maximum thickness of 30 µm, which can be achieved by meeting a wet-deposit thickness of 50 µm.
In addition, there is pressure to achieve tighter tolerances on flatness, and higher standards of surface finish. Component vendors and packaging specialists must also reach high throughput and repeatability to achieve economies of scale and satisfy growing world demand at consumer price points.
Flatness and Coplanarity
Wafer processing houses require six-sigma repeatability at close tolerances to maintain yield during subsequent wafer bonding processes or at die attachment after singulation. At the bonding or die-attach stage, thermo-compression is frequently used to fully cure the B-stage die-attach epoxy, or to fuse a glass frit bonding medium. This typically requires total-thickness variation to be in the region of 7 µm to prevent die damage. Failure to meet this tolerance will promote defects such as cracking or over-stressing, leading to latent faults in completed components.
As coating thicknesses are progressively reduced, it is important to specify requirements for the coating’s surface finish. In stacked-die assembly, for example, the B-stage epoxy layer performs bonding and die-protection functions. A high-quality surface finish with low roughness is required to avoid air inclusion at the epoxy/wafer boundaries. If air becomes trapped due to peaks and troughs in the wafer coating, it will expand during later reflow of the component, leading to high device failure rates at the end of line (EOL).
Process Development for Advanced Wafer Coating
Wafer back-side coating with a wet epoxy is sometimes spin-coated to distribute liquid adhesive dispensed onto the wafer center. However, printer-based processes have demonstrated six-sigma repeatability for deposits of 50 µm ±5 µm, hosted on equipment similar to in-line screen printers used in high-volume surface-mount assembly. Printer-based wafer back-side coating is capable of high throughput, and the platform can also be reassigned to other chip-scale assembly processes - solder ball attachment, wafer bumping with paste, or over-molding. Figure 2 shows how a printer can be integrated with an automated wafer loader/unloader.
Figure 1. Wafers coated using a back-side coating process.
To meet specified targets on thickness, flatness, and surface finish when developing a screen printing process for wafer coating, the design is fundamentally influenced by material properties. Depending on the material’s thixotropic characteristics, precision emulsion screens built using fine-gauge polyester or stainless steel mesh can achieve a total-thickness variation of less than 10% at low deposit thicknesses. With some materials, however, the surface of the deposit may retain the mesh pattern of the screen after snap-off. This is particularly true when aiming for a very thin deposited layer, as in stacked-die applications. Depending on the application, this may be acceptable, and subsequent die placement and thermo-compression to final-cure the B-stage adhesive may negate the effect of the variations in surface topology.
Figure 2. A printer that is integrated with an automated wafer loader/unloader.
On the other hand, where the surface finish is outside the limits required for the process at hand, a different technique may be required. For example, a fine-gauge metal stencil, used in combination with a suitable squeegee, enables a smoother surface finish. However, a large stencil aperture is necessary to coat wafers in standard sizes up to 300 mm (Figure 3).
Screen printing using large-aperture stencils such as this requires specialized equipment. Large-aperture processes are particularly prone to squeegees scooping the print medium. As the squeegee flexes during printing, it produces a concave surface in the deposited epoxy. This effect is particularly noticeable at low deposit thicknesses used in wafer-level processes.
To combat these effects, squeegees for wafer-level printing at ultra-low thicknesses, using materials such as glass frit and B-stage epoxies, are adopting new geometries, contours, and production techniques. The conventional squeegee profile for surface mount pre-placement has a square edge, presenting a sharp profile at the stencil surface. Varying the squeegee’s angle of attack can influence the process window, for example, by allowing a wider range of settings for print speed. Among emerging techniques to reduce these scooping effects, the initial goal has been to increase the rigidity of the squeegee to prevent the blade edge from sagging into the aperture.
Focus on Squeegee Performance
Research has focused on optimizing squeegee material properties and determining the most suitable squeegee shape to minimize deflection of the blade during printing; thereby effectively eliminating scooping as a challenge to wafer-level printing. A cleanroom-grade, non-oxidizing stainless steel has been used, for example, to achieve a squeegee that is inherently more rigid than those used for conventional surface-mount printing. In addition, experiments with squeegee profiles have resulted in adoption of a rounded-edge blade.
Surface preparations also have significant impact on meeting requirements for a high-surface finish in printed epoxy. A sequence of flattening and polishing techniques, for example, is necessary to produce a squeegee capable of achieving a smooth epoxy coating to meet stringent requirements on total-thickness variation for advanced packaging demands.
However, this new avenue of squeegee development has introduced its own set of challenges. Squeegee movement produces a bow wave in the deposited epoxy, leaving ripples in the deposited surface. In some cases, these can be of sufficient total height to prevent the coating from meeting the specified tolerance on surface finish and flatness. Further investigation into squeegee design is ongoing, to fully characterize the relationship between total-thickness variation, surface finish, print speed, and squeegee profile. Success will enable wafer coating at thicknesses significantly lower than 50 µm, using suitable materials.
Wafer Support for Volume Production
As with any mass deposition process, wafer support is critical to meeting six-sigma accuracy and repeatability demands.
Experimental wafer pallets have been used in laboratory projects to develop wafer-level printing processes, and also to prove processes for precision deposition onto flexible substrates, including fuel-cell membranes. These have provided a test bed for techniques to achieve surface-plate flatness, to ensure true and repeatable coplanarity when working with sub-100-µm-gauge wafers. Various methods for applying vacuum to retain the wafer during printing have also been investigated.
Figure 3. This fine-gauge metal stencil is designed for back-side coating of 300-mm wafers.
For high-speed deposition of precision wafer coatings in a production environment, a lightweight, low-cost wafer support solution is required. Machined-aluminium pallets, for example, have low mass to facilitate positioning and alignment within the screen printing machine, and can be produced quickly and cost-effectively. On the other hand, development is ongoing to further improve accuracy and maximize robustness and durability. Current avenues of research include optimized machining techniques to create vacuum channels without impairing the surface characteristics and rigidity of the pallet (Figure 4).
Depositing an over-mold on the non-passive side of the wafer, although not subject to quite the same stringent demands for a very thin deposit, also challenges screen printing process engineers to reduce tolerances on deposit thickness and surface flatness. Screen printing presents a compelling economic argument for over-molding, due to its low cost-of-ownership and the potential for high throughput. However, close control of over-mold thickness is necessary so that end users can easily assemble onto PCBs or other substrates using high-speed automated pick-and-place equipment. Large variations in package thickness will lead to high instances of mis-picks, part rejection, and z-height errors leading to component damage.
Figure 4. The machining of vacuum channels into the surface of a metal pallet for wafer back-side coating applications.
A high level of surface flatness is also required, for easier laser marking of the component identifier and serial number. A high-quality surface, possessing a flat area spanning the maximum possible proportion of the component top-side area, is also required to enable a reliable vacuum seal against the pick-and-place nozzle during assembly.
Major component packaging processes, including underfill and adhesives application, are now being performed at wafer level to achieve significant reductions in component dimensions and cost-per-unit. In the search for suitable high-speed, repeatable processes to deposit these layers according to tightly defined requirements, a number of precision printing techniques are available to package developers. These allow package designers and process engineers to choose from a number of technologies including precision screens, large-aperture stencils, and emerging high-rigidity squeegees to fine-tune wafer-level processes.
BY STEVE WATKIN, semiconductor and alternative applications manager; NEIL SHORT, mechanical design engineer, semiconductor packaging technologies; and CLIVE ASHMORE, global applied process engineering manager, may be contacted at DEK International, Granby Industrial Estate, Weymouth, Dorset DT4 9TH, UK; 44/1305 760760; E-mail: email@example.com, firstname.lastname@example.org, and email@example.com.