Advanced Packaging talked with IMEC’s Ann Witvrouw about recent developments in MEMS and CMOS processing, and how the technology could lead to advanced packaging techniques across the spectrum of MEMS structures.
Novel wafer-level 3D technologies will enable cell phone and other mobile equipment designers to achieve greater circuit density and/or significant cost savings, versus designs that make use of chips in traditional leadframe packages.
Nearly a year after the presentation of “A Case for Socket Reuse,” by Paul Gaschke of IBM, at the 2006 Burn-in and Test Socket (BiTS) Workshop, I wondered whether compression-mount sockets (which enabled the socket reuse he described) were seeing more widespread acceptance and application by users, and being added to suppliers’ product portfolios.
While research in nano-transistors and nanotube wiring has been widely publicized, few seem to realize that a less glamorous application of nanotechnology in microelectronics device packaging appears closer to commercial reality.
The die-attach layer has two main functions: mechanical fixation of the die on its substrate, and dissipation of heat generated in the die. Especially in power and high-power applications, generated heat density is high.